1 /* $NetBSD: dm9000.c,v 1.41 2025/10/04 04:44:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* based on sys/dev/ic/cs89x0.c */ 30 /* 31 * Copyright (c) 2004 Christopher Gilbert 32 * All rights reserved. 33 * 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The name of the company nor the name of the author may be used to 40 * endorse or promote products derived from this software without specific 41 * prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright 1997 58 * Digital Equipment Corporation. All rights reserved. 59 * 60 * This software is furnished under license and may be used and 61 * copied only in accordance with the following terms and conditions. 62 * Subject to these conditions, you may download, copy, install, 63 * use, modify and distribute this software in source and/or binary 64 * form. No title or ownership is transferred hereby. 65 * 66 * 1) Any source code used, modified or distributed must reproduce 67 * and retain this copyright notice and list of conditions as 68 * they appear in the source file. 69 * 70 * 2) No right is granted to use any trade name, trademark, or logo of 71 * Digital Equipment Corporation. Neither the "Digital Equipment 72 * Corporation" name nor any trademark or logo of Digital Equipment 73 * Corporation may be used to endorse or promote products derived 74 * from this software without the prior written permission of 75 * Digital Equipment Corporation. 76 * 77 * 3) This software is provided "AS-IS" and any express or implied 78 * warranties, including but not limited to, any implied warranties 79 * of merchantability, fitness for a particular purpose, or 80 * non-infringement are disclaimed. In no event shall DIGITAL be 81 * liable for any damages whatsoever, and in particular, DIGITAL 82 * shall not be liable for special, indirect, consequential, or 83 * incidental damages or damages for lost profits, loss of 84 * revenue or loss of use, whether such damages arise in contract, 85 * negligence, tort, under statute, in equity, at law or otherwise, 86 * even if advised of the possibility of such damage. 87 */ 88 89 #include <sys/cdefs.h> 90 91 #include <sys/param.h> 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 #include <sys/device.h> 95 #include <sys/mbuf.h> 96 #include <sys/sockio.h> 97 #include <sys/errno.h> 98 #include <sys/cprng.h> 99 #include <sys/rndsource.h> 100 #include <sys/kernel.h> 101 #include <sys/systm.h> 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_ether.h> 106 #include <net/if_media.h> 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include <net/bpf.h> 110 111 #include <dev/ic/dm9000var.h> 112 #include <dev/ic/dm9000reg.h> 113 114 #if 1 115 #undef DM9000_DEBUG 116 #undef DM9000_TX_DEBUG 117 #undef DM9000_TX_DATA_DEBUG 118 #undef DM9000_RX_DEBUG 119 #undef DM9000_RX_DATA_DEBUG 120 #else 121 #define DM9000_DEBUG 122 #define DM9000_TX_DEBUG 123 #define DM9000_TX_DATA_DEBUG 124 #define DM9000_RX_DEBUG 125 #define DM9000_RX_DATA_DEBUG 126 #endif 127 128 #ifdef DM9000_DEBUG 129 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 130 #else 131 #define DPRINTF(s) do {} while (/*CONSTCOND*/0) 132 #endif 133 134 #ifdef DM9000_TX_DEBUG 135 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 136 #else 137 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 138 #endif 139 140 #ifdef DM9000_RX_DEBUG 141 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 142 #else 143 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0) 144 #endif 145 146 #ifdef DM9000_RX_DATA_DEBUG 147 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 148 #else 149 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 150 #endif 151 152 #ifdef DM9000_TX_DATA_DEBUG 153 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0) 154 #else 155 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0) 156 #endif 157 158 static void dme_reset(struct dme_softc *); 159 static int dme_init(struct ifnet *); 160 static void dme_stop(struct ifnet *, int); 161 static void dme_start(struct ifnet *); 162 static int dme_ioctl(struct ifnet *, u_long, void *); 163 164 static void dme_set_rcvfilt(struct dme_softc *); 165 static void mii_statchg(struct ifnet *); 166 static void lnkchg(struct dme_softc *); 167 static void phy_tick(void *); 168 static int mii_readreg(device_t, int, int, uint16_t *); 169 static int mii_writereg(device_t, int, int, uint16_t); 170 171 static void dme_prepare(struct ifnet *); 172 static void dme_transmit(struct ifnet *); 173 static void dme_receive(struct ifnet *); 174 175 static int pkt_read_2(struct dme_softc *, struct mbuf **); 176 static int pkt_write_2(struct dme_softc *, struct mbuf *); 177 static int pkt_read_1(struct dme_softc *, struct mbuf **); 178 static int pkt_write_1(struct dme_softc *, struct mbuf *); 179 #define PKT_READ(ii,m) (*(ii)->sc_pkt_read)((ii),(m)) 180 #define PKT_WRITE(ii,m) (*(ii)->sc_pkt_write)((ii),(m)) 181 182 #define ETHER_IS_ONE(x) \ 183 (((x)[0] & (x)[1] & (x)[2] & (x)[3] & (x)[4] & (x)[5]) == 255) 184 #define ETHER_IS_ZERO(x) \ 185 (((x)[0] | (x)[1] | (x)[2] | (x)[3] | (x)[4] | (x)[5]) == 0) 186 187 int 188 dme_attach(struct dme_softc *sc, const uint8_t *notusedanymore) 189 { 190 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 191 struct mii_data *mii = &sc->sc_mii; 192 struct ifmedia *ifm = &mii->mii_media; 193 uint8_t b[2]; 194 uint16_t io_mode; 195 uint8_t enaddr[ETHER_ADDR_LEN]; 196 197 dme_read_c(sc, DM9000_VID0, b, 2); 198 sc->sc_vendor_id = le16toh((uint16_t)b[1] << 8 | b[0]); 199 dme_read_c(sc, DM9000_PID0, b, 2); 200 sc->sc_product_id = le16toh((uint16_t)b[1] << 8 | b[0]); 201 202 /* TODO: Check the vendor ID as well */ 203 if (sc->sc_product_id != 0x9000) { 204 panic("dme_attach: product id mismatch (0x%hx != 0x9000)", 205 sc->sc_product_id); 206 } 207 #if 1 || DM9000_DEBUG 208 { 209 dme_read_c(sc, DM9000_PAB0, enaddr, 6); 210 aprint_normal_dev(sc->sc_dev, 211 "DM9000 was configured with MAC address: %s\n", 212 ether_sprintf(enaddr)); 213 } 214 #endif 215 if (! ether_getaddr(sc->sc_dev, enaddr)) { 216 /* 217 * If we did not get an externally configure address, 218 * try to read one from the current setup, before 219 * resetting the chip. 220 */ 221 dme_read_c(sc, DM9000_PAB0, enaddr, 6); 222 if (ETHER_IS_ONE(enaddr) || ETHER_IS_ZERO(enaddr)) { 223 /* make a random MAC address */ 224 uint32_t maclo = 0x00f2 | (cprng_strong32() << 16); 225 uint32_t machi = cprng_strong32(); 226 enaddr[0] = maclo; 227 enaddr[1] = maclo >> 8; 228 enaddr[2] = maclo >> 16; 229 enaddr[3] = maclo >> 26; 230 enaddr[4] = machi; 231 enaddr[5] = machi >> 8; 232 } 233 } 234 /* TODO: perform explicit EEPROM read op if it's available */ 235 236 dme_reset(sc); 237 238 mii->mii_ifp = ifp; 239 mii->mii_readreg = mii_readreg; 240 mii->mii_writereg = mii_writereg; 241 mii->mii_statchg = mii_statchg; 242 243 /* assume davicom PHY at 1. ext PHY could be hooked but only at 0-3 */ 244 sc->sc_ethercom.ec_mii = mii; 245 ifmedia_init(ifm, 0, ether_mediachange, ether_mediastatus); 246 mii_attach(sc->sc_dev, mii, 0xffffffff, 1 /* PHY 1 */, 247 MII_OFFSET_ANY, 0); 248 if (LIST_FIRST(&mii->mii_phys) == NULL) { 249 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 250 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 251 } else 252 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 253 ifm->ifm_media = ifm->ifm_cur->ifm_media; 254 255 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 256 ifp->if_softc = sc; 257 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 258 ifp->if_init = dme_init; 259 ifp->if_start = dme_start; 260 ifp->if_stop = dme_stop; 261 ifp->if_ioctl = dme_ioctl; 262 ifp->if_watchdog = NULL; /* no watchdog used */ 263 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 264 IFQ_SET_READY(&ifp->if_snd); 265 266 if_attach(ifp); 267 ether_ifattach(ifp, enaddr); 268 if_deferred_start_init(ifp, NULL); 269 270 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 271 RND_TYPE_NET, RND_FLAG_DEFAULT); 272 273 /* might be unnecessary as link change interrupt works well */ 274 callout_init(&sc->sc_link_callout, 0); 275 callout_setfunc(&sc->sc_link_callout, phy_tick, sc); 276 277 io_mode = (dme_read(sc, DM9000_ISR) & 278 DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT; 279 280 /* frame body read/write ops in 2 byte quantity or byte-wise. */ 281 DPRINTF(("DM9000 Operation Mode: ")); 282 switch (io_mode) { 283 case DM9000_MODE_8BIT: 284 DPRINTF(("8-bit mode")); 285 sc->sc_data_width = 1; 286 sc->sc_pkt_write = pkt_write_1; 287 sc->sc_pkt_read = pkt_read_1; 288 break; 289 case DM9000_MODE_16BIT: 290 DPRINTF(("16-bit mode")); 291 sc->sc_data_width = 2; 292 sc->sc_pkt_write = pkt_write_2; 293 sc->sc_pkt_read = pkt_read_2; 294 break; 295 case DM9000_MODE_32BIT: 296 DPRINTF(("32-bit mode")); 297 sc->sc_data_width = 4; 298 panic("32bit mode is unsupported\n"); 299 break; 300 default: 301 DPRINTF(("Invalid mode")); 302 break; 303 } 304 DPRINTF(("\n")); 305 306 return 0; 307 } 308 309 int 310 dme_detach(struct dme_softc *sc) 311 { 312 return 0; 313 } 314 315 /* Software Initialize/Reset of the DM9000 */ 316 static void 317 dme_reset(struct dme_softc *sc) 318 { 319 uint8_t misc; 320 321 /* We only re-initialized the PHY in this function the first time it is 322 * called. */ 323 if (!sc->sc_phy_initialized) { 324 /* PHY Reset */ 325 mii_writereg(sc->sc_dev, 1, MII_BMCR, BMCR_RESET); 326 327 /* PHY Power Down */ 328 misc = dme_read(sc, DM9000_GPR); 329 dme_write(sc, DM9000_GPR, misc | DM9000_GPR_PHY_PWROFF); 330 } 331 332 /* Reset the DM9000 twice, as described in section 2 of the Programming 333 * Guide. 334 * The PHY is initialized and enabled between those two resets. 335 */ 336 337 /* Software Reset */ 338 dme_write(sc, DM9000_NCR, 339 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 340 delay(20); 341 dme_write(sc, DM9000_NCR, 0x0); 342 343 if (!sc->sc_phy_initialized) { 344 /* PHY Enable */ 345 misc = dme_read(sc, DM9000_GPR); 346 dme_write(sc, DM9000_GPR, misc & ~DM9000_GPR_PHY_PWROFF); 347 misc = dme_read(sc, DM9000_GPCR); 348 dme_write(sc, DM9000_GPCR, misc | DM9000_GPCR_GPIO0_OUT); 349 350 dme_write(sc, DM9000_NCR, 351 DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL); 352 delay(20); 353 dme_write(sc, DM9000_NCR, 0x0); 354 } 355 356 /* Select internal PHY, no wakeup event, no collision mode, 357 * normal loopback mode. 358 */ 359 dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL); 360 361 /* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/ 362 dme_read(sc, DM9000_NSR); 363 364 /* Enable wraparound of read/write pointer, frame received latch, 365 * and frame transmitted latch. 366 */ 367 dme_write(sc, DM9000_IMR, 368 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 369 370 dme_write(sc, DM9000_RCR, 371 DM9000_RCR_DIS_CRC | DM9000_RCR_DIS_LONG | DM9000_RCR_WTDIS); 372 373 sc->sc_phy_initialized = 1; 374 } 375 376 static int 377 dme_init(struct ifnet *ifp) 378 { 379 struct dme_softc *sc = ifp->if_softc; 380 381 dme_stop(ifp, 0); 382 dme_reset(sc); 383 dme_write_c(sc, DM9000_PAB0, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 384 dme_set_rcvfilt(sc); 385 (void)ether_mediachange(ifp); 386 387 sc->txbusy = sc->txready = 0; 388 389 ifp->if_flags |= IFF_RUNNING; 390 callout_schedule(&sc->sc_link_callout, hz); 391 392 return 0; 393 } 394 395 /* Configure multicast filter */ 396 static void 397 dme_set_rcvfilt(struct dme_softc *sc) 398 { 399 struct ethercom *ec = &sc->sc_ethercom; 400 struct ifnet *ifp = &ec->ec_if; 401 struct ether_multi *enm; 402 struct ether_multistep step; 403 uint8_t mchash[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* 64bit mchash */ 404 uint32_t h = 0; 405 int rcr; 406 407 rcr = dme_read(sc, DM9000_RCR); 408 rcr &= ~(DM9000_RCR_PRMSC | DM9000_RCR_ALL); 409 dme_write(sc, DM9000_RCR, rcr &~ DM9000_RCR_RXEN); 410 411 ETHER_LOCK(ec); 412 if (ifp->if_flags & IFF_PROMISC) { 413 ec->ec_flags |= ETHER_F_ALLMULTI; 414 ETHER_UNLOCK(ec); 415 /* run promisc. mode */ 416 rcr |= DM9000_RCR_PRMSC; 417 goto update; 418 } 419 ec->ec_flags &= ~ETHER_F_ALLMULTI; 420 ETHER_FIRST_MULTI(step, ec, enm); 421 while (enm != NULL) { 422 if (memcpy(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 423 /* 424 * We must listen to a range of multicast addresses. 425 * For now, just accept all multicasts, rather than 426 * trying to set only those filter bits needed to match 427 * the range. (At this time, the only use of address 428 * ranges is for IP multicast routing, for which the 429 * range is big enough to require all bits set.) 430 */ 431 ec->ec_flags |= ETHER_F_ALLMULTI; 432 ETHER_UNLOCK(ec); 433 memset(mchash, 0xff, sizeof(mchash)); /* necessary? */ 434 /* accept all multicast frame */ 435 rcr |= DM9000_RCR_ALL; 436 goto update; 437 } 438 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 439 /* 3(5:3) and 3(2:0) sampling to have uint8_t[8] */ 440 mchash[h / 8] |= 1 << (h % 8); 441 ETHER_NEXT_MULTI(step, enm); 442 } 443 ETHER_UNLOCK(ec); 444 /* DM9000 receive filter is always on */ 445 mchash[7] |= 0x80; /* to catch bcast frame */ 446 update: 447 dme_write_c(sc, DM9000_MAB0, mchash, sizeof(mchash)); 448 dme_write(sc, DM9000_RCR, rcr | DM9000_RCR_RXEN); 449 return; 450 } 451 452 void 453 lnkchg(struct dme_softc *sc) 454 { 455 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 456 struct ifmediareq ifmr; 457 458 ether_mediastatus(ifp, &ifmr); 459 } 460 461 static void 462 mii_statchg(struct ifnet *ifp) 463 { 464 struct dme_softc *sc = ifp->if_softc; 465 struct mii_data *mii = &sc->sc_mii; 466 uint8_t fcr, ncr; 467 468 #if 0 469 const uint8_t Mbps[2] = { 10, 100 }; 470 uint8_t nsr = dme_read(sc, DM9000_NSR); 471 int spd = Mbps[!!(nsr & DM9000_NSR_SPEED)]; 472 /* speed/duplexity available also in reg 0x11 of internal PHY */ 473 if (nsr & DM9000_NSR_LINKST) 474 printf("link up,spd%d", spd); 475 else 476 printf("link down"); 477 478 /* show resolved mii(4) parameters */ 479 printf("MII spd%d", 480 (int)(sc->sc_ethercom.ec_if.if_baudrate / IF_Mbps(1))); 481 if (mii->mii_media_active & IFM_FDX) 482 printf(",full-duplex"); 483 printf("\n"); 484 #endif 485 486 /* Adjust duplexity and PAUSE flow control. */ 487 fcr = dme_read(sc, DM9000_FCR) &~ DM9000_FCR_FLCE; 488 ncr = dme_read(sc, DM9000_NCR) &~ DM9000_NCR_FDX; 489 if ((mii->mii_media_active & IFM_FDX) 490 && (mii->mii_media_active & IFM_FLOW)) { 491 fcr |= DM9000_FCR_FLCE; 492 ncr |= DM9000_NCR_FDX; 493 } 494 dme_write(sc, DM9000_FCR, fcr); 495 dme_write(sc, DM9000_NCR, ncr); 496 } 497 498 static void 499 phy_tick(void *arg) 500 { 501 struct dme_softc *sc = arg; 502 struct mii_data *mii = &sc->sc_mii; 503 int s; 504 505 s = splnet(); 506 mii_tick(mii); 507 splx(s); 508 509 callout_schedule(&sc->sc_link_callout, hz); 510 } 511 512 static int 513 mii_readreg(device_t self, int phy, int reg, uint16_t *val) 514 { 515 struct dme_softc *sc = device_private(self); 516 517 if (phy != 1) 518 return EINVAL; 519 520 /* Select Register to read*/ 521 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 522 (reg & DM9000_EPAR_EROA_MASK)); 523 /* Select read operation (DM9000_EPCR_ERPRR) from the PHY */ 524 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY); 525 526 /* Wait until access to PHY has completed */ 527 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 528 ; 529 530 /* Reset ERPRR-bit */ 531 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 532 533 *val = dme_read(sc, DM9000_EPDRL) | (dme_read(sc, DM9000_EPDRH) << 8); 534 return 0; 535 } 536 537 static int 538 mii_writereg(device_t self, int phy, int reg, uint16_t val) 539 { 540 struct dme_softc *sc = device_private(self); 541 542 if (phy != 1) 543 return EINVAL; 544 545 /* Select Register to write */ 546 dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY + 547 (reg & DM9000_EPAR_EROA_MASK)); 548 549 /* Write data to the two data registers */ 550 dme_write(sc, DM9000_EPDRL, val & 0xFF); 551 dme_write(sc, DM9000_EPDRH, (val >> 8) & 0xFF); 552 553 /* Select write operation (DM9000_EPCR_ERPRW) from the PHY */ 554 dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY); 555 556 /* Wait until access to PHY has completed */ 557 while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE) 558 ; 559 560 /* Reset ERPRR-bit */ 561 dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY); 562 563 return 0; 564 } 565 566 void 567 dme_stop(struct ifnet *ifp, int disable) 568 { 569 struct dme_softc *sc = ifp->if_softc; 570 571 /* Not quite sure what to do when called with disable == 0 */ 572 if (disable) { 573 /* Disable RX */ 574 dme_write(sc, DM9000_RCR, 0x0); 575 } 576 mii_down(&sc->sc_mii); 577 callout_stop(&sc->sc_link_callout); 578 579 ifp->if_flags &= ~IFF_RUNNING; 580 ifp->if_timer = 0; 581 } 582 583 static void 584 dme_start(struct ifnet *ifp) 585 { 586 struct dme_softc *sc = ifp->if_softc; 587 588 if ((ifp->if_flags & IFF_RUNNING) == 0) { 589 return; 590 } 591 if (!sc->txready) { 592 dme_prepare(ifp); 593 } 594 if (sc->txbusy) { 595 /* 596 * We need to wait until the current frame has 597 * been transmitted. 598 */ 599 return; 600 } 601 if (sc->txready) { 602 /* We are ready to transmit right away */ 603 dme_transmit(ifp); 604 } 605 dme_prepare(ifp); /* Prepare next one */ 606 } 607 608 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */ 609 static void 610 dme_prepare(struct ifnet *ifp) 611 { 612 struct dme_softc *sc = ifp->if_softc; 613 uint16_t length; 614 struct mbuf *m; 615 616 KASSERT(!sc->txready); 617 618 IFQ_DEQUEUE(&ifp->if_snd, m); 619 if (m == NULL) { 620 TX_DPRINTF(("dme_prepare: Nothing to transmit\n")); 621 return; /* Nothing to transmit */ 622 } 623 624 /* Element has now been removed from the queue, so we better send it */ 625 626 bpf_mtap(ifp, m, BPF_D_OUT); 627 628 /* Setup the DM9000 to accept the writes, and then write each buf in 629 the chain. */ 630 631 TX_DATA_DPRINTF(("dme_prepare: Writing data: ")); 632 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD); 633 length = PKT_WRITE(sc, m); 634 bpf_mtap(ifp, m, BPF_D_OUT); 635 TX_DATA_DPRINTF(("\n")); 636 637 if (length % sc->sc_data_width != 0) 638 panic("dme_prepare: length is not compatible with IO_MODE"); 639 640 sc->txready_length = length; 641 sc->txready = 1; 642 m_freem(m); 643 } 644 645 /* Transmit prepared data */ 646 static void 647 dme_transmit(struct ifnet *ifp) 648 { 649 struct dme_softc *sc = ifp->if_softc; 650 651 TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n", 652 sc->txready, sc->txbusy)); 653 654 /* prime frame length first */ 655 dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff); 656 dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff); 657 /* read isr next */ 658 dme_read(sc, DM9000_ISR); 659 /* finally issue a request to send */ 660 dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ); 661 sc->txready = 0; 662 sc->txbusy = 1; 663 sc->txready_length = 0; 664 } 665 666 /* Receive data */ 667 static void 668 dme_receive(struct ifnet *ifp) 669 { 670 struct dme_softc *sc = ifp->if_softc; 671 struct mbuf *m; 672 uint8_t avail, rsr; 673 674 DPRINTF(("inside dme_receive\n")); 675 676 /* frame has just arrived, retrieve it */ 677 /* called right after Rx frame available interrupt */ 678 do { 679 /* "no increment" read to get the avail byte without 680 moving past it. */ 681 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, 682 DM9000_MRCMDX); 683 /* Read twice */ 684 avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 685 avail = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 686 avail &= 03; /* 1:0 we only want these bits */ 687 if (avail == 01) { 688 /* Read with address increment. */ 689 bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, 690 DM9000_MRCMD); 691 rsr = PKT_READ(sc, &m); 692 if (m == NULL) { 693 /* failed to allocate a receive buffer */ 694 RX_DPRINTF(("dme_receive: " 695 "Error allocating buffer\n")); 696 if_statinc(ifp, if_ierrors); 697 continue; 698 } 699 if (rsr & (DM9000_RSR_CE | DM9000_RSR_PLE)) { 700 /* Error while receiving the frame, 701 * discard it and keep track of counters 702 */ 703 RX_DPRINTF(("dme_receive: " 704 "Error reciving frame\n")); 705 if_statinc(ifp, if_ierrors); 706 continue; 707 } 708 if (rsr & DM9000_RSR_LCS) { 709 if_statinc(ifp, if_collisions); 710 continue; 711 } 712 /* pick and forward this frame to ifq */ 713 if_percpuq_enqueue(ifp->if_percpuq, m); 714 } else if (avail != 00) { 715 /* Should this be logged somehow? */ 716 printf("%s: Resetting chip\n", 717 device_xname(sc->sc_dev)); 718 dme_reset(sc); 719 break; 720 } 721 } while (avail == 01); 722 /* frame received successfully */ 723 } 724 725 int 726 dme_intr(void *arg) 727 { 728 struct dme_softc *sc = arg; 729 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 730 uint8_t isr, nsr, tsr; 731 732 DPRINTF(("dme_intr: Begin\n")); 733 734 /* Disable interrupts */ 735 dme_write(sc, DM9000_IMR, DM9000_IMR_PAR); 736 737 isr = dme_read(sc, DM9000_ISR); 738 dme_write(sc, DM9000_ISR, isr); /* write to clear */ 739 740 if (isr & DM9000_ISR_PRS) { 741 KASSERT(ifp->if_flags & IFF_RUNNING); 742 dme_receive(ifp); 743 } 744 if (isr & DM9000_ISR_LNKCHNG) 745 lnkchg(sc); 746 if (isr & DM9000_ISR_PTS) { 747 tsr = 0x01; /* Initialize to an error value */ 748 749 /* A frame has been transmitted */ 750 sc->txbusy = 0; 751 752 nsr = dme_read(sc, DM9000_NSR); 753 if (nsr & DM9000_NSR_TX1END) { 754 tsr = dme_read(sc, DM9000_TSR1); 755 TX_DPRINTF(("dme_intr: Sent using channel 0\n")); 756 } else if (nsr & DM9000_NSR_TX2END) { 757 tsr = dme_read(sc, DM9000_TSR2); 758 TX_DPRINTF(("dme_intr: Sent using channel 1\n")); 759 } 760 761 if (tsr == 0x0) { 762 /* Frame successfully sent */ 763 if_statinc(ifp, if_opackets); 764 } else { 765 if_statinc(ifp, if_oerrors); 766 } 767 768 /* If we have nothing ready to transmit, prepare something */ 769 if (!sc->txready) 770 dme_prepare(ifp); 771 772 if (sc->txready) 773 dme_transmit(ifp); 774 775 /* Prepare the next frame */ 776 dme_prepare(ifp); 777 778 if_schedule_deferred_start(ifp); 779 } 780 781 /* Enable interrupts again */ 782 dme_write(sc, DM9000_IMR, 783 DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM); 784 785 DPRINTF(("dme_intr: End\n")); 786 787 return (isr != 0); 788 } 789 790 static int 791 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data) 792 { 793 struct dme_softc *sc = ifp->if_softc; 794 struct ifreq *ifr = (struct ifreq *)data; 795 struct ifmedia *ifm = &sc->sc_mii.mii_media; 796 int s, error; 797 798 s = splnet(); 799 switch (cmd) { 800 case SIOCSIFMEDIA: 801 /* Flow control requires full-duplex mode. */ 802 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 803 (ifr->ifr_media & IFM_FDX) == 0) 804 ifr->ifr_media &= ~IFM_ETH_FMASK; 805 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 806 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 807 ifr->ifr_media |= 808 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 809 } 810 } 811 error = ifmedia_ioctl(ifp, ifr, ifm, cmd); 812 break; 813 default: 814 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 815 break; 816 error = 0; 817 if (cmd == SIOCSIFCAP) 818 error = if_init(ifp); 819 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 820 ; 821 else if (ifp->if_flags && IFF_RUNNING) { 822 /* Address list has changed, reconfigure filter */ 823 dme_set_rcvfilt(sc); 824 } 825 break; 826 } 827 splx(s); 828 return error; 829 } 830 831 static struct mbuf * 832 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length) 833 { 834 struct dme_softc *sc = ifp->if_softc; 835 struct mbuf *m; 836 int pad, quantum; 837 838 quantum = sc->sc_data_width; 839 MGETHDR(m, M_DONTWAIT, MT_DATA); 840 if (m == NULL) 841 return NULL; 842 843 m_set_rcvif(m, ifp); 844 /* Ensure that we always allocate an even number of 845 * bytes in order to avoid writing beyond the buffer 846 */ 847 m->m_pkthdr.len = frame_length + (frame_length % quantum); 848 pad = ALIGN(sizeof(struct ether_header)) - 849 sizeof(struct ether_header); 850 /* All our frames have the CRC attached */ 851 m->m_flags |= M_HASFCS; 852 if (m->m_pkthdr.len + pad > MHLEN) { 853 MCLGET(m, M_DONTWAIT); 854 if ((m->m_flags & M_EXT) == 0) { 855 m_freem(m); 856 return NULL; 857 } 858 } 859 860 m->m_data += pad; 861 m->m_len = frame_length + (frame_length % quantum); 862 863 return m; 864 } 865 866 static int 867 pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain) 868 { 869 int left_over_count = 0; /* Number of bytes from previous mbuf, which 870 need to be written with the next.*/ 871 uint16_t left_over_buf = 0; 872 int length = 0; 873 struct mbuf *buf; 874 uint8_t *write_ptr; 875 876 /* We expect that the DM9000 has been setup to accept writes before 877 this function is called. */ 878 879 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 880 int to_write = buf->m_len; 881 882 length += to_write; 883 884 write_ptr = buf->m_data; 885 while (to_write > 0 || 886 (buf->m_next == NULL && left_over_count > 0)) { 887 if (left_over_count > 0) { 888 uint8_t b = 0; 889 DPRINTF(("pkt_write_16: " 890 "Writing left over byte\n")); 891 892 if (to_write > 0) { 893 b = *write_ptr; 894 to_write--; 895 write_ptr++; 896 897 DPRINTF(("Took single byte\n")); 898 } else { 899 DPRINTF(("Leftover in last run\n")); 900 length++; 901 } 902 903 /* Does shift direction depend on endianness? */ 904 left_over_buf = left_over_buf | (b << 8); 905 906 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 907 sc->dme_data, left_over_buf); 908 TX_DATA_DPRINTF(("%02X ", left_over_buf)); 909 left_over_count = 0; 910 } else if ((long)write_ptr % 2 != 0) { 911 /* Misaligned data */ 912 DPRINTF(("pkt_write_16: " 913 "Detected misaligned data\n")); 914 left_over_buf = *write_ptr; 915 left_over_count = 1; 916 write_ptr++; 917 to_write--; 918 } else { 919 int i; 920 uint16_t *dptr = (uint16_t *)write_ptr; 921 922 /* A block of aligned data. */ 923 for (i = 0; i < to_write / 2; i++) { 924 /* buf will be half-word aligned 925 * all the time 926 */ 927 bus_space_write_2(sc->sc_iot, 928 sc->sc_ioh, sc->dme_data, *dptr); 929 TX_DATA_DPRINTF(("%02X %02X ", 930 *dptr & 0xFF, (*dptr >> 8) & 0xFF)); 931 dptr++; 932 } 933 934 write_ptr += i * 2; 935 if (to_write % 2 != 0) { 936 DPRINTF(("pkt_write_16: " 937 "to_write %% 2: %d\n", 938 to_write % 2)); 939 left_over_count = 1; 940 /* XXX: Does this depend on 941 * the endianness? 942 */ 943 left_over_buf = *write_ptr; 944 945 write_ptr++; 946 to_write--; 947 DPRINTF(("pkt_write_16: " 948 "to_write (after): %d\n", 949 to_write)); 950 DPRINTF(("pkt_write_16: i * 2: %d\n", 951 i*2)); 952 } 953 to_write -= i * 2; 954 } 955 } /* while (...) */ 956 } /* for (...) */ 957 958 return length; 959 } 960 961 static int 962 pkt_read_2(struct dme_softc *sc, struct mbuf **outBuf) 963 { 964 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 965 uint8_t rx_status; 966 struct mbuf *m; 967 uint16_t data; 968 uint16_t frame_length; 969 uint16_t i; 970 uint16_t *buf; 971 972 data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data); 973 rx_status = data & 0xFF; 974 975 frame_length = bus_space_read_2(sc->sc_iot, 976 sc->sc_ioh, sc->dme_data); 977 if (frame_length > ETHER_MAX_LEN) { 978 printf("Got frame of length: %d\n", frame_length); 979 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 980 panic("Something is rotten"); 981 } 982 RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n", 983 rx_status, frame_length)); 984 985 m = dme_alloc_receive_buffer(ifp, frame_length); 986 if (m == NULL) { 987 /* 988 * didn't get a receive buffer, so we read the rest of the 989 * frame, throw it away and return an error 990 */ 991 for (i = 0; i < frame_length; i += 2) { 992 data = bus_space_read_2(sc->sc_iot, 993 sc->sc_ioh, sc->dme_data); 994 } 995 *outBuf = NULL; 996 return 0; 997 } 998 999 buf = mtod(m, uint16_t*); 1000 1001 RX_DPRINTF(("dme_receive: ")); 1002 1003 for (i = 0; i < frame_length; i += 2) { 1004 data = bus_space_read_2(sc->sc_iot, 1005 sc->sc_ioh, sc->dme_data); 1006 if ( (frame_length % 2 != 0) && 1007 (i == frame_length - 1) ) { 1008 data = data & 0xff; 1009 RX_DPRINTF((" L ")); 1010 } 1011 *buf = data; 1012 buf++; 1013 RX_DATA_DPRINTF(("%02X %02X ", data & 0xff, 1014 (data >> 8) & 0xff)); 1015 } 1016 1017 RX_DATA_DPRINTF(("\n")); 1018 RX_DPRINTF(("Read %d bytes\n", i)); 1019 1020 *outBuf = m; 1021 return rx_status; 1022 } 1023 1024 static int 1025 pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain) 1026 { 1027 int length = 0, i; 1028 struct mbuf *buf; 1029 uint8_t *write_ptr; 1030 1031 /* 1032 * We expect that the DM9000 has been setup to accept writes before 1033 * this function is called. 1034 */ 1035 1036 for (buf = bufChain; buf != NULL; buf = buf->m_next) { 1037 int to_write = buf->m_len; 1038 1039 length += to_write; 1040 1041 write_ptr = buf->m_data; 1042 for (i = 0; i < to_write; i++) { 1043 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1044 sc->dme_data, *write_ptr); 1045 write_ptr++; 1046 } 1047 } /* for (...) */ 1048 1049 return length; 1050 } 1051 1052 static int 1053 pkt_read_1(struct dme_softc *sc, struct mbuf **outBuf) 1054 { 1055 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1056 uint8_t rx_status; 1057 struct mbuf *m; 1058 uint8_t *buf; 1059 uint16_t frame_length; 1060 uint16_t i, reg; 1061 uint8_t data; 1062 1063 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1064 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1065 rx_status = reg & 0xFF; 1066 1067 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1068 reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8; 1069 frame_length = reg; 1070 1071 if (frame_length > ETHER_MAX_LEN) { 1072 printf("Got frame of length: %d\n", frame_length); 1073 printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN); 1074 panic("Something is rotten"); 1075 } 1076 RX_DPRINTF(("dme_receive: " 1077 "rx_statux: 0x%x, frame_length: %d\n", 1078 rx_status, frame_length)); 1079 1080 m = dme_alloc_receive_buffer(ifp, frame_length); 1081 if (m == NULL) { 1082 /* 1083 * didn't get a receive buffer, so we read the rest of the 1084 * frame, throw it away and return an error 1085 */ 1086 for (i = 0; i < frame_length; i++ ) { 1087 data = bus_space_read_2(sc->sc_iot, 1088 sc->sc_ioh, sc->dme_data); 1089 } 1090 *outBuf = NULL; 1091 return 0; 1092 } 1093 1094 buf = mtod(m, uint8_t *); 1095 1096 RX_DPRINTF(("dme_receive: ")); 1097 for (i = 0; i< frame_length; i += 1) { 1098 data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data); 1099 *buf = data; 1100 buf++; 1101 RX_DATA_DPRINTF(("%02X ", data)); 1102 } 1103 1104 RX_DATA_DPRINTF(("\n")); 1105 RX_DPRINTF(("Read %d bytes\n", i)); 1106 1107 *outBuf = m; 1108 return rx_status; 1109 } 1110
Indexes created Sun Oct 12 05:10:08 GMT 2025