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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
Makefile 53 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
56 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
57 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
58 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
59 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
64 CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
65 CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 65 #include "dml/display_mode_vba.h"
2265 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2266 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2502 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2503 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2506 if (vlevel > context->bw_ctx.dml.soc.num_states)
2510 context->bw_ctx.dml.vba.maxMpcComb = 0;
2513 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2520 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 40 #include "dml/dml1_display_rq_dlg_calc.h"
449 struct display_mode_lib *dml = (struct display_mode_lib *)__UNCONST(&dc->dml); local
488 // dc->dml.logger = pool->base.logger;
496 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
497 dml1_extract_rq_regs(dml, rq_regs, rq_param);
499 dml,
1052 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1053 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1268 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 64 #include "dml/display_mode_vba.h"
982 struct display_mode_lib *dml,
986 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
988 ASSERT(vlevel < dml->soc.num_states);
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
992 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
994 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
995 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
996 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
998 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
Makefile 31 DC_LIBS += dcn10 dml
dc.h 42 #include "dml/display_mode_lib.h"
476 * for DML. Unlike the debug option for forcing
514 struct display_mode_lib dml; member in struct:dc
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc.c 733 /* Creation of current_state must occur after dc->dml
735 * on creation it copies the contents of dc->dml
1363 * initialize and obtain IP and SOC the base DML instance from DC is
1367 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1549 * and DML calculation
1572 * thus need to run DML to calculate RQ settings
2470 struct display_mode_lib *dml; local
2493 dml = kzalloc(sizeof(struct display_mode_lib),
2496 ASSERT(dml);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 350 struct display_mode_lib dml; member in struct:bw_context
358 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 1428 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1435 struct display_mode_lib *dml = &dc->dml; local
1437 dml->ip.max_num_dpp = 3;
1565 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1568 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
  /src/sys/modules/amdgpu/
Makefile 122 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml
123 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml/dcn20
124 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml/dcn21

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