HomeSort by: relevance | last modified time | path
    Searched refs:dml_ceil (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_dml_common_defs.c 39 double ceil = dml_ceil(a, 1);
dml_inline_defs.h 70 static inline double dml_ceil(double a, double granularity) function in typeref:typename:double
amdgpu_display_mode_vba.c 861 dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
862 dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
863 + dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio, 1)
864 * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal,
865 dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal));
868 dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio),
869 dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidth / 2.0 / 2.0, 1
    [all...]
amdgpu_dml1_display_rq_dlg_calc.c 190 *max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 */
434 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
674 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
910 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
1842 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_mode_vba_21.c 760 *VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1);
813 *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY;
814 *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC;
816 *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY;
817 *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC;
820 prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto;
837 Tvm_oto_lines = dml_ceil(4 * Tvm_oto / LineTime, 1) / 4.0;
838 Tr0_oto_lines = dml_ceil(4 * Tr0_oto / LineTime, 1) / 4.0;
839 Tsw_oto_lines = dml_ceil(4 * Tsw_oto / LineTime, 1) / 4.0
    [all...]
amdgpu_display_rq_dlg_calc_21.c 438 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
674 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
1621 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(
1626 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1773 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_mode_vba_20.c 551 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
606 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
607 + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
662 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
664 * dml_ceil(BytePerPixelDETC, 2))
770 * dml_ceil(
775 * dml_ceil(
814 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
837 *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
852 *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1)
    [all...]
amdgpu_display_mode_vba_20v2.c 508 DataFabricLineDeliveryTimeLuma = SwathWidthSingleDPPY * SwathHeightY * dml_ceil(BytePerPixelDETY, 1) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneLuma / TotalDataReadBandwidth);
512 DataFabricLineDeliveryTimeChroma = SwathWidthSingleDPPY / 2 * SwathHeightC * dml_ceil(BytePerPixelDETC, 2) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneChroma / TotalDataReadBandwidth);
614 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
666 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
667 + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
722 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
724 * dml_ceil(BytePerPixelDETC, 2))
830 * dml_ceil(
835 * dml_ceil(
874 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1)
    [all...]
amdgpu_display_rq_dlg_calc_20.c 446 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
1521 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
1526 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1659 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
amdgpu_display_rq_dlg_calc_20v2.c 446 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
1522 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
1527 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1660 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)

Completed in 82 milliseconds