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  /src/share/misc/
Makefile 6 country domains dot.clang-format operator \
26 DOMAIN_URL= https://www.iana.org/domains/root/db
27 update-domains:
38 ) > domains ; \
  /src/tests/lib/libc/gen/
t_setdomainname.c 43 static const char domains[][MAXHOSTNAMELEN] = { variable
62 for (i = 0; i < __arraycount(domains); i++) {
66 ATF_REQUIRE(setdomainname(domains[i],sizeof(domains[i])) == 0);
68 ATF_REQUIRE(strcmp(domains[i], name) == 0);
  /src/sys/sys/
domain.h 100 __link_set_add_data(domains, name)
102 #define DOMAIN_FOREACH(dom) STAILQ_FOREACH(dom, &domains, dom_link)
103 extern struct domainhead domains;
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/engine/
pm.h 14 struct list_head domains; member in struct:nvkm_pm
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
nouveau_nvkm_subdev_clk_g84.c 37 .domains = {
priv.h 18 struct nvkm_domain domains[]; member in struct:nvkm_clk_func
nouveau_nvkm_subdev_clk_nv04.c 74 .domains = {
nouveau_nvkm_subdev_clk_base.c 87 const struct nvkm_domain *domain = clk->domains;
232 const struct nvkm_domain *domain = clk->domains;
380 const struct nvkm_domain *clock = clk->domains - 1;
437 const struct nvkm_domain *domain = clk->domains - 1;
626 const struct nvkm_domain *clock = clk->domains;
709 clk->domains = func->domains;
nouveau_nvkm_subdev_clk_nv40.c 215 .domains = {
nouveau_nvkm_subdev_clk_mcp77.c 409 .domains = {
nouveau_nvkm_subdev_clk_gm20b.c 891 .domains = {
908 .domains = {
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display_power.c 494 int refs = hweight64(power_well->desc->domains &
2102 /* Requeue the work if more domains were async put meanwhile. */
2175 * corresponding power domains.
2549 * ICL PW_0/PG_0 domains (HW/DMC control):
2554 * ICL PW_1/PG_1 domains (HW/DMC control):
2767 .domains = POWER_DOMAIN_MASK,
2784 .domains = POWER_DOMAIN_MASK,
2790 .domains = I830_PIPES_POWER_DOMAINS,
2828 .domains = POWER_DOMAIN_MASK,
2834 .domains = HSW_DISPLAY_POWER_DOMAINS
    [all...]
intel_display_power.h 90 * the power domains framework must be assigned a unique ID. The rest of power
155 u64 domains; member in struct:i915_power_well_desc
242 for_each_if((__power_well)->desc->domains & (__domain_mask))
246 for_each_if((__power_well)->desc->domains & (__domain_mask))
  /src/sys/arch/epoc32/stand/e32boot/ldd/
epoc32.cpp 44 TUint domains; local
56 domains = ALL_DOMAINS(0xf);
57 __asm("mcr p15, 0, %0, c3, c0" : : "r"(domains));
  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_uncore.h 78 enum forcewake_domains domains);
80 enum forcewake_domains domains);
108 enum forcewake_domains domains; member in struct:intel_forcewake_range
148 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
171 /* Iterate over initialised fw domains */
232 enum forcewake_domains domains);
234 enum forcewake_domains domains);
239 enum forcewake_domains domains);
241 enum forcewake_domains domains);
intel_uncore.c 491 return fw; /* track the lost user forcewake domains */
643 * @fw_domains: forcewake domains to get reference on
646 * Normal register access will handle the forcewake domains automatically.
648 * forcewake domains this function should be called at the beginning of the
650 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
715 * @fw_domains: forcewake domains to get reference on
754 * @fw_domains: forcewake domains to put references
757 * domains obtained by intel_uncore_forcewake_get().
775 * @fw_domains: forcewake domains to get reference on
898 * The list of FW domains depends on the SKU in gen11+ so w
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
mt2712e.dtsi 752 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
805 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
820 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
869 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
884 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
1005 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1014 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1025 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1036 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1045 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>
    [all...]
mt7622.dtsi 534 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
731 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
748 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
823 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
861 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
894 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
939 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
985 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
  /src/sys/kern/
uipc_domain.c 70 struct domainhead domains = STAILQ_HEAD_INITIALIZER(domains); variable in typeref:struct:domainhead
86 /* ensure successful linkage even without any domains in link sets */
88 __link_set_add_rodata(domains,domain_dummy);
104 __link_set_decl(domains, struct domain);
111 * Add all of the domains. Make sure the PF_ROUTE
115 __link_set_foreach(dpp, domains) {
132 * after all domains have been attached.
146 STAILQ_INSERT_TAIL(&domains, dp, dom_link);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/
clk.h 89 const struct nvkm_domain *domains; member in struct:nvkm_clk
  /src/usr.sbin/ypbind/
ypbind.c 116 /* the list of all domains */
117 static struct domain *domains; variable in typeref:struct:domain
280 for (dom = domains; dom != NULL; dom = dom->dom_next)
305 * domains.
341 * reject domains for which there is no ypservers file.
355 dom->dom_next = domains;
356 domains = dom;
505 for (dom = domains; dom != NULL; dom = dom->dom_next)
620 * carry the XID of one of the domains we know about; but
716 /* Reject invalid domains. *
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/pm/
nouveau_nvkm_engine_pm_base.c 46 list_for_each_entry(dom, &pm->domains, head)
72 list_for_each_entry(dom, &pm->domains, head) {
260 list_for_each_entry(dom, &pm->domains, head)
801 list_add_tail(&dom->head, &pm->domains);
843 list_for_each_entry_safe(dom, next_dom, &pm->domains, head) {
869 INIT_LIST_HEAD(&pm->domains);
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_gem.c 215 /* we restrict allowed domains on nv50+ to only the types
303 uint32_t domains = valid_domains & nvbo->valid_domains & local
307 if (!domains)
316 if ((domains & NOUVEAU_GEM_DOMAIN_VRAM) &&
320 else if ((domains & NOUVEAU_GEM_DOMAIN_GART) &&
324 else if (domains & NOUVEAU_GEM_DOMAIN_VRAM)
476 NV_PRINTK(err, cli, "invalid valid domains: 0x%08x\n",
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gem.c 248 /* reject invalid gem domains */
249 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
253 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
274 (u32)(0xffffffff & args->in.domains),
739 info.domains = robj->preferred_domains;
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/
nouveau_nvkm_engine_device_ctrl.c 99 domain = clk->domains;

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