| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dpp.h | 127 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
131 struct dpp *dpp_base,
194 struct dpp *dpp_base,
198 struct dpp *dpp_base,
201 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
205 struct dpp *dpp_base,
212 void (*dpp_full_bypass)(struct dpp *dpp_base);
215 struct dpp *dpp_base,
219 struct dpp *dpp_base,
227 struct dpp *dpp_base,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp_cm.c | 56 struct dpp *dpp_base)
58 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
62 if (dpp_base->ctx->dc->debug.cm_in_bypass)
70 struct dpp *dpp_base,
75 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
91 struct dpp *dpp_base,
98 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
122 struct dpp *dpp_base,
127 dpp1_power_on_degamma_lut(dpp_base, true);
128 dpp2_enable_cm_block(dpp_base);
[all...] |
| amdgpu_dcn20_dpp.c | 56 void dpp20_read_state(struct dpp *dpp_base,
59 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
81 struct dpp *dpp_base,
84 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
96 struct dpp *dpp_base,
101 struct dpp *dpp_base,
108 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
239 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry);
241 dpp2_program_input_csc(dpp_base, color_space, select, NULL);
250 dpp2_power_on_obuf(dpp_base, true)
[all...] |
| amdgpu_dcn20_hwseq.c | 782 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn20_set_blend_lut
792 &dpp_base->regamma_params, false);
793 blend_lut = &dpp_base->regamma_params;
796 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
804 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn20_set_shaper_3dlut
814 &dpp_base->shaper_params, true);
815 shaper_lut = &dpp_base->shaper_params;
819 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut)
835 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn20_set_input_transfer_func
[all...] |
| dcn20_dpp.h | 713 void dpp20_read_state(struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
729 struct dpp *dpp_base,
735 struct dpp *dpp_base, const struct pwl_params *params);
738 struct dpp *dpp_base,
742 struct dpp *dpp_base,
746 struct dpp *dpp_base,
756 struct dpp *dpp_base,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp.c | 99 void dpp_read_state(struct dpp *dpp_base,
102 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
208 void dpp_reset(struct dpp *dpp_base)
210 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
224 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
226 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
244 dpp1_cm_power_on_regamma_lut(dpp_base, true);
245 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
248 dpp1_cm_program_regamma_luta_settings(dpp_base, params);
250 dpp1_cm_program_regamma_lutb_settings(dpp_base, params)
[all...] |
| amdgpu_dcn10_dpp_cm.c | 166 struct dpp *dpp_base,
169 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
245 struct dpp *dpp_base,
248 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
315 struct dpp *dpp_base,
318 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
323 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
326 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
333 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
338 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
[all...] |
| dcn10_dpp.h | 1372 struct dpp *dpp_base,
1376 struct dpp *dpp_base,
1383 struct dpp *dpp_base,
1398 struct dpp *dpp_base,
1402 struct dpp *dpp_base,
1406 struct dpp *dpp_base,
1410 struct dpp *dpp_base,
1416 struct dpp *dpp_base,
1420 struct dpp *dpp_base,
1426 struct dpp *dpp_base,
[all...] |
| amdgpu_dcn10_dpp_dscl.c | 173 struct dpp *dpp_base,
179 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
530 struct dpp *dpp_base,
534 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
536 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
669 struct dpp *dpp_base,
673 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
675 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale)
[all...] |
| amdgpu_dcn10_hw_sequencer.c | 1457 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; local in function:dcn10_set_input_transfer_func
1461 if (dpp_base == NULL)
1468 !dpp_base->ctx->dc->debug.always_use_regamma
1471 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1474 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1478 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1481 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC)
[all...] |
