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    Searched refs:dppclk (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr.h 90 uint32_t dppclk; member in struct:clk_state_registers_and_bypass
112 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
119 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 268 uint32_t dppclk : 1; member in struct:pipe_update_flags::__anon10ef0c660308
dcn_calcs.h 438 float dppclk; member in struct:dcn_bw_internal_vars
606 int max_dchub_topscl_throughput; /*pixels/dppclk*/
607 int max_pscl_tolb_throughput; /*pixels/dppclk*/
608 int max_lb_tovscl_throughput; /*pixels/dppclk*/
609 int max_vscl_tohscl_throughput; /*pixels/dppclk*/
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calc_auto.c 325 /*maximum dispclk/dppclk support check*/
1184 /*dispclk and dppclk calculation*/
1228 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
1305 v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
1317 v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
1428 v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]);
1431 v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]);
1648 v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
1659 v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);
1660 v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k]
    [all...]
amdgpu_dcn_calcs.c 150 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
151 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
152 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
153 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
484 input.clks_cfg.dppclk_mhz = v->dppclk;
1035 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1656 "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1657 "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1658 "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1659 "max_vscl_tohscl_throughput: %d pixels/dppclk\n
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 1186 new_pipe->update_flags.bits.dppclk = 1;
1243 /* Detect dppclk change */
1245 new_pipe->update_flags.bits.dppclk = 1;
1321 if (pipe_ctx->update_flags.bits.dppclk)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr.c 159 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
180 // increase per DPP DTO before lowering global dppclk
184 // increase global DPPCLK before lowering per DPP DTO
268 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
354 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",

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