| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 113 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
115 int dpp_inst, dppclk_khz, prev_dppclk_khz; local in function:dcn20_update_clocks_update_dpp_dto
121 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
125 if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) {
127 clk_mgr->dccg, dpp_inst, dppclk_khz);
135 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
234 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz))
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr.c | 49 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
52 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
97 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
126 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 161 if (new_clocks->dppclk_khz < 100000)
162 new_clocks->dppclk_khz = 100000;
165 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
166 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
168 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
182 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
186 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 358 context->bw_ctx.bw.dcn.clk.dppclk_khz,
366 context->bw_ctx.bw.dcn.clk.dppclk_khz,
|
| amdgpu_dc.c | 2697 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 226 int dppclk_khz; member in struct:dcn_fe_bandwidth
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 279 int dppclk_khz; member in struct:dc_clocks
296 int bw_dppclk_khz; /*a copy of dppclk_khz*/
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 483 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
|
| amdgpu_dcn10_hw_sequencer.c | 452 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
456 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
2250 bool should_divided_by_2 = context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2262 pipe_ctx->plane_res.bw.dppclk_khz);
2264 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
3296 current_clocks->dppclk_khz = clk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2796 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2842 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2843 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2844 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2851 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
| amdgpu_dcn20_hwseq.c | 1244 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 1149 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1396 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
|
