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    Searched refs:dprefclk_khz (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
amdgpu_dce120_clk_mgr.c 141 clk_mgr->base.dprefclk_khz = 600000;
148 clk_mgr->base.dprefclk_khz = 625000;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr.h 159 uint32_t dprefclk_khz; member in struct:clk_states
194 int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes member in struct:clk_mgr
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr_vbios_smu.c 126 clk_mgr->base.dprefclk_khz / 1000);
amdgpu_rv1_clk_mgr.c 274 clk_mgr->base.dprefclk_khz = 600000;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
amdgpu_rn_clk_mgr_vbios_smu.c 117 clk_mgr->base.dprefclk_khz / 1000);
amdgpu_rn_clk_mgr.c 394 s->dprefclk_khz = sb.dprefclk * 1000;
745 clk_mgr->base.dprefclk_khz = 600000;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 454 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
489 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
amdgpu_dce_clk_mgr.c 164 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_clk_mgr.c 183 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz);
935 clk_mgr_dce->dprefclk_khz = 600000;
956 clk_mgr_dce->dprefclk_khz = 625000;

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