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    Searched refs:dsc_enc_caps (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
amdgpu_dc_dsc.c 225 struct dsc_enc_caps *dsc_enc_caps,
230 memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));
233 dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);
235 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
244 const struct dsc_enc_caps *dsc_enc_caps,
246 struct dsc_enc_caps *dsc_common_caps)
251 memset(dsc_common_caps, 0, sizeof(struct dsc_enc_caps));
892 struct dsc_enc_caps dsc_enc_caps; local in function:dc_dsc_compute_bandwidth_range
920 struct dsc_enc_caps dsc_enc_caps; local in function:dc_dsc_compute_config
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
dsc.h 77 struct dsc_enc_caps { struct
90 void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dsc.c 45 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
111 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
113 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
115 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
116 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
117 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
118 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
120 dsc_enc_caps->lb_bit_depth = 13
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