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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770_dma.c 39 * @dst_offset: dst GPU address
48 uint64_t src_offset, uint64_t dst_offset,
80 radeon_ring_write(ring, dst_offset & 0xfffffffc);
82 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
85 dst_offset += cur_size_in_dw * 4;
radeon_evergreen_dma.c 104 * @dst_offset: dst GPU address
114 uint64_t dst_offset,
146 radeon_ring_write(ring, dst_offset & 0xfffffffc);
148 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
151 dst_offset += cur_size_in_dw * 4;
radeon_si_dma.c 228 * @dst_offset: dst GPU address
237 uint64_t src_offset, uint64_t dst_offset,
269 radeon_ring_write(ring, lower_32_bits(dst_offset));
271 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
274 dst_offset += cur_size_in_bytes;
radeon_evergreen_cs.c 2833 u64 src_offset, dst_offset, dst2_offset; local in function:evergreen_dma_cs_parse
2858 dst_offset = radeon_get_ib_value(p, idx+1);
2859 dst_offset <<= 8;
2866 dst_offset = radeon_get_ib_value(p, idx+1);
2867 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2877 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2879 dst_offset, radeon_bo_size(dst_reloc->robj));
2900 dst_offset = radeon_get_ib_value(p, idx+1);
2901 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2907 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj))
    [all...]
radeon_r600_dma.c 440 * @dst_offset: dst GPU address
449 uint64_t src_offset, uint64_t dst_offset,
481 radeon_ring_write(ring, dst_offset & 0xfffffffc);
483 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
486 dst_offset += cur_size_in_dw * 4;
radeon_r600_cs.c 2386 u64 src_offset, dst_offset; local in function:r600_dma_cs_parse
2409 dst_offset = radeon_get_ib_value(p, idx+1);
2410 dst_offset <<= 8;
2415 dst_offset = radeon_get_ib_value(p, idx+1);
2416 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2422 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2424 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2448 dst_offset = radeon_get_ib_value(p, idx+5);
2449 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2459 dst_offset = radeon_get_ib_value(p, idx+1)
    [all...]
radeon_r200.c 90 uint64_t dst_offset,
120 radeon_ring_write(ring, dst_offset);
123 dst_offset += cur_size;
radeon_asic.h 89 uint64_t dst_offset,
160 uint64_t dst_offset,
350 uint64_t src_offset, uint64_t dst_offset,
354 uint64_t src_offset, uint64_t dst_offset,
476 uint64_t src_offset, uint64_t dst_offset,
550 uint64_t src_offset, uint64_t dst_offset,
728 uint64_t src_offset, uint64_t dst_offset,
799 uint64_t src_offset, uint64_t dst_offset,
803 uint64_t src_offset, uint64_t dst_offset,
radeon_cik_sdma.c 576 * @dst_offset: dst GPU address
585 uint64_t src_offset, uint64_t dst_offset,
621 radeon_ring_write(ring, lower_32_bits(dst_offset));
622 radeon_ring_write(ring, upper_32_bits(dst_offset));
624 dst_offset += cur_size_in_bytes;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma.h 93 uint64_t dst_offset,
108 uint64_t dst_offset,
amdgpu_ttm.h 103 uint64_t dst_offset, uint32_t byte_count,
amdgpu_sdma_v2_4.c 1199 * @dst_offset: dst GPU address
1208 uint64_t dst_offset,
1217 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1218 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1226 * @dst_offset: dst GPU address
1233 uint64_t dst_offset,
1237 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1238 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
amdgpu_si_dma.c 773 * @dst_offset: dst GPU address
782 uint64_t dst_offset,
787 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
789 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff;
798 * @dst_offset: dst GPU address
805 uint64_t dst_offset,
810 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
812 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16;
amdgpu_cik_sdma.c 1311 * @dst_offset: dst GPU address
1320 uint64_t dst_offset,
1328 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1329 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1337 * @dst_offset: dst GPU address
1344 uint64_t dst_offset,
1348 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1349 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
amdgpu_sdma_v3_0.c 1637 * @dst_offset: dst GPU address
1646 uint64_t dst_offset,
1655 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1656 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1664 * @dst_offset: dst GPU address
1671 uint64_t dst_offset,
1675 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1676 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
amdgpu_sdma_v5_0.c 1657 * @dst_offset: dst GPU address
1666 uint64_t dst_offset,
1675 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1676 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1684 * @dst_offset: dst GPU address
1691 uint64_t dst_offset,
1695 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1696 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
  /src/sys/external/bsd/drm2/dist/drm/qxl/
qxl_ioctl.c 82 uint32_t dst_offset; member in struct:qxl_reloc_info
97 reloc_page = qxl_bo_kmap_atomic_page(qdev, info->dst_bo, info->dst_offset & PAGE_MASK);
98 *(uint64_t *)(reloc_page + (info->dst_offset & ~PAGE_MASK)) = qxl_bo_physical_address(qdev,
113 reloc_page = qxl_bo_kmap_atomic_page(qdev, info->dst_bo, info->dst_offset & PAGE_MASK);
114 *(uint32_t *)(reloc_page + (info->dst_offset & ~PAGE_MASK)) = id;
237 reloc_info[i].dst_offset = reloc.dst_offset;
240 reloc_info[i].dst_offset = reloc.dst_offset + release->release_offset;
  /src/sys/external/bsd/drm2/dist/drm/vmwgfx/
vmwgfx_blit.c 357 * @dst_offset: Destination copy start offset from start of bo.
362 u32 dst_offset,
370 u32 dst_page = dst_offset >> PAGE_SHIFT;
372 u32 dst_page_offset = dst_offset & ~PAGE_MASK;
420 dst_offset += copy_size;
431 * @dst_offset: Destination offset of blit start in bytes.
451 u32 dst_offset, u32 dst_stride,
461 u32 j, initial_line = dst_offset / dst_stride;
497 diff->line_offset = dst_offset % dst_stride;
498 ret = vmw_bo_cpu_blit_line(&d, dst_offset, src_offset, w)
    [all...]
vmwgfx_stdu.c 585 u32 src_offset, dst_offset; local in function:vmw_stdu_bo_cpu_commit
600 dst_offset = ddirty->top * dst_pitch + ddirty->left * stdu->cpp;
610 swap(src_offset, dst_offset);
613 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch,
1302 u32 src_offset, dst_offset; local in function:vmw_stdu_bo_populate_update_cpu
1317 dst_offset = bb->y1 * dst_pitch + bb->x1 * stdu->cpp;
1324 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch, src_bo,
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_object_blt.c 212 u64 src_offset, dst_offset; local in function:intel_emit_vma_copy_blt
239 dst_offset = dst->node.start;
250 *cmd++ = lower_32_bits(dst_offset);
251 *cmd++ = upper_32_bits(dst_offset);
261 *cmd++ = lower_32_bits(dst_offset);
262 *cmd++ = upper_32_bits(dst_offset);
271 *cmd++ = dst_offset;
280 dst_offset += size;
  /src/sys/external/bsd/drm2/dist/include/uapi/drm/
qxl_drm.h 77 __u64 dst_offset; /* offset in dest handle */ member in struct:drm_qxl_reloc
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_bo.c 877 u64 dst_offset = mem->vma[1].addr; local in function:nvc0_bo_move_copy
892 OUT_RING (chan, upper_32_bits(dst_offset));
893 OUT_RING (chan, lower_32_bits(dst_offset));
903 dst_offset += (PAGE_SIZE * line_count);
915 u64 dst_offset = mem->vma[1].addr; local in function:nvc0_bo_move_m2mf
928 OUT_RING (chan, upper_32_bits(dst_offset));
929 OUT_RING (chan, lower_32_bits(dst_offset));
942 dst_offset += (PAGE_SIZE * line_count);
954 u64 dst_offset = mem->vma[1].addr; local in function:nva3_bo_move_copy
969 OUT_RING (chan, upper_32_bits(dst_offset));
1045 u64 dst_offset = mem->vma[1].addr; local in function:nv50_bo_move_m2mf
1139 u32 dst_offset = new_reg->start << PAGE_SHIFT; local in function:nv04_bo_move_m2mf
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
intel_uc_fw.c 438 static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
458 intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, dst_offset);
490 * @dst_offset: destination offset
497 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
514 err = uc_fw_xfer(uc_fw, dst_offset, dma_flags);
  /src/sys/arch/amiga/dev/
grf_rt.c 1303 u_long src_offset, dst_offset;
1322 dst_offset = op->dst_x + op->dst_y * gp->g_display.gd_fbwidth;
1331 if (src_offset < dst_offset)
1335 dst_offset += tot;
1340 dst_bank_lo = (dst_offset >> 6) & 0xff;
1341 dst_bank_hi = (dst_offset >> 14) & 0xff;
1350 if (src_offset < dst_offset)
  /src/sys/external/bsd/ena-com/
ena_eth_com.c 85 u32 dst_offset; local in function:ena_com_write_bounce_buffer_to_dev
88 dst_offset = dst_tail_mask * llq_info->desc_list_entry_size;
96 ENA_MEMCPY_TO_DEVICE_64(io_sq->desc_addr.pbuf_dev_addr + dst_offset,

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