| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 913 double dst_y_per_row_flip; local in function:dml_rq_dlg_get_dlg_params
1152 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1165 dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip);
1485 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1493 dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
1516 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1518 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htota
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 867 double dst_y_per_row_flip; local in function:dml20_rq_dlg_get_dlg_params
1102 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1412 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1438 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1440 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1444 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
1446 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
|
| amdgpu_display_rq_dlg_calc_20v2.c | 867 double dst_y_per_row_flip; local in function:dml20v2_rq_dlg_get_dlg_params
1103 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1413 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1439 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1441 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1445 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
1447 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 234 "DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x%0x\n",
235 dlg_regs.dst_y_per_row_flip);
|
| display_mode_structs.h | 430 unsigned int dst_y_per_row_flip; member in struct:_vcs_dpi_display_dlg_regs_st
|
| display_mode_vba.h | 76 dml_get_pipe_attr_decl(dst_y_per_row_flip);
|
| amdgpu_display_mode_vba.c | 136 dst_y_per_row_flip,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 268 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
|
| amdgpu_dcn10_hw_sequencer.c | 235 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_hwseq.c | 1270 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1288 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
|
| amdgpu_dcn20_hubp.c | 267 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
|
