1 /* $NetBSD: if_enet_imx.c,v 1.8 2025/10/04 04:14:56 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_enet_imx.c,v 1.8 2025/10/04 04:14:56 thorpej Exp $"); 31 32 #include "opt_fdt.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 38 #include <arm/imx/if_enetreg.h> 39 #include <arm/imx/if_enetvar.h> 40 41 #include <dev/fdt/fdtvar.h> 42 43 struct enet_fdt_softc { 44 struct enet_softc sc_enet; 45 46 struct fdtbus_gpio_pin *sc_pin_reset; 47 }; 48 49 CFATTACH_DECL_NEW(enet_fdt, sizeof(struct enet_fdt_softc), 50 enet_match, enet_attach, NULL, NULL); 51 52 static const struct device_compatible_entry compat_data[] = { 53 /* compatible imxtype */ 54 { .compat = "fsl,imx6q-fec", .value = 6 }, 55 { .compat = "fsl,imx6sx-fec", .value = 7 }, 56 DEVICE_COMPAT_EOL 57 }; 58 59 static int enet_init_clocks(struct enet_softc *); 60 static void enet_phy_reset(struct enet_fdt_softc *, const int); 61 static int enet_phy_id(struct enet_softc *, const int); 62 static void *enet_intr_establish(struct enet_softc *, int, u_int); 63 64 int 65 enet_match(device_t parent, cfdata_t cf, void *aux) 66 { 67 struct fdt_attach_args * const faa = aux; 68 69 return of_compatible_match(faa->faa_phandle, compat_data); 70 } 71 72 void 73 enet_attach(device_t parent, device_t self, void *aux) 74 { 75 struct enet_fdt_softc * const efsc = device_private(self); 76 struct enet_softc *sc = &efsc->sc_enet; 77 struct fdt_attach_args * const faa = aux; 78 const int phandle = faa->faa_phandle; 79 bus_space_tag_t bst = faa->faa_bst; 80 bus_space_handle_t bsh; 81 bus_addr_t addr; 82 bus_size_t size; 83 int error; 84 85 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 86 aprint_error(": couldn't get enet registers\n"); 87 return; 88 } 89 90 error = bus_space_map(bst, addr, size, 0, &bsh); 91 if (error) { 92 aprint_error(": couldn't map enet registers: %d\n", error); 93 return; 94 } 95 96 sc->sc_clk_ipg = fdtbus_clock_get(phandle, "ipg"); 97 if (sc->sc_clk_ipg == NULL) { 98 aprint_error(": couldn't get clock ipg\n"); 99 goto failure; 100 } 101 sc->sc_clk_enet = fdtbus_clock_get(phandle, "ahb"); 102 if (sc->sc_clk_enet == NULL) { 103 aprint_error(": couldn't get clock ahb\n"); 104 goto failure; 105 } 106 sc->sc_clk_enet_ref = fdtbus_clock_get(phandle, "ptp"); 107 if (sc->sc_clk_enet_ref == NULL) { 108 aprint_error(": couldn't get clock ptp\n"); 109 goto failure; 110 } 111 112 if (fdtbus_clock_enable(phandle, "enet_clk_ref", false) != 0) { 113 aprint_error(": couldn't enable clock enet_clk_ref\n"); 114 goto failure; 115 } 116 if (fdtbus_clock_enable(phandle, "enet_out", false) != 0) { 117 aprint_error(": couldn't enable clock enet_out\n"); 118 goto failure; 119 } 120 121 aprint_naive("\n"); 122 aprint_normal(": Gigabit Ethernet Controller\n"); 123 124 sc->sc_dev = self; 125 sc->sc_iot = bst; 126 sc->sc_ioh = bsh; 127 sc->sc_dmat = faa->faa_dmat; 128 129 sc->sc_imxtype = of_compatible_lookup(phandle, compat_data)->value; 130 sc->sc_unit = 0; 131 sc->sc_phyid = enet_phy_id(sc, phandle); 132 133 const char *phy_mode = fdtbus_get_string(phandle, "phy-mode"); 134 if (phy_mode == NULL) { 135 aprint_error(": missing 'phy-mode' property\n"); 136 goto failure; 137 } 138 139 if (strcmp(phy_mode, "rgmii-txid") == 0) { 140 device_setprop_bool(self, "tx_internal_delay", true); 141 sc->sc_rgmii = 1; 142 } else if (strcmp(phy_mode, "rgmii-rxid") == 0) { 143 device_setprop_bool(self, "rx_internal_delay", true); 144 sc->sc_rgmii = 1; 145 } else if (strcmp(phy_mode, "rgmii-id") == 0) { 146 device_setprop_bool(self, "tx_internal_delay", true); 147 device_setprop_bool(self, "rx_internal_delay", true); 148 sc->sc_rgmii = 1; 149 } else if (strcmp(phy_mode, "rgmii") == 0) { 150 sc->sc_rgmii = 1; 151 } else { 152 sc->sc_rgmii = 0; 153 } 154 155 sc->sc_ih = enet_intr_establish(sc, phandle, 0); 156 if (sc->sc_ih == NULL) 157 goto failure; 158 159 if (sc->sc_imxtype == 7) { 160 sc->sc_ih2 = enet_intr_establish(sc, phandle, 1); 161 sc->sc_ih3 = enet_intr_establish(sc, phandle, 2); 162 if (sc->sc_ih2 == NULL || sc->sc_ih3 == NULL) 163 goto failure; 164 } 165 166 enet_init_clocks(sc); 167 sc->sc_clock = clk_get_rate(sc->sc_clk_ipg); 168 169 enet_phy_reset(efsc, phandle); 170 171 if (enet_attach_common(self) != 0) 172 goto failure; 173 174 return; 175 176 failure: 177 bus_space_unmap(bst, bsh, size); 178 return; 179 } 180 181 static void * 182 enet_intr_establish(struct enet_softc *sc, int phandle, u_int index) 183 { 184 char intrstr[128]; 185 char xname[16]; 186 void *ih; 187 188 if (!fdtbus_intr_str(phandle, index, intrstr, sizeof(intrstr))) { 189 aprint_error_dev(sc->sc_dev, "failed to decode interrupt %d\n", 190 index); 191 return NULL; 192 } 193 194 snprintf(xname, sizeof(xname), "%s #%u", device_xname(sc->sc_dev), 195 index); 196 ih = fdtbus_intr_establish_xname(phandle, index, IPL_NET, 0, 197 enet_intr, sc, xname); 198 if (ih == NULL) { 199 aprint_error_dev(sc->sc_dev, "failed to establish interrupt on %s\n", 200 intrstr); 201 return NULL; 202 } 203 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 204 205 return ih; 206 } 207 208 static int 209 enet_init_clocks(struct enet_softc *sc) 210 { 211 int error; 212 213 error = clk_enable(sc->sc_clk_ipg); 214 if (error) { 215 aprint_error_dev(sc->sc_dev, "couldn't enable ipg: %d\n", error); 216 return error; 217 } 218 error = clk_enable(sc->sc_clk_enet); 219 if (error) { 220 aprint_error_dev(sc->sc_dev, "couldn't enable enet: %d\n", error); 221 return error; 222 } 223 error = clk_enable(sc->sc_clk_enet_ref); 224 if (error) { 225 aprint_error_dev(sc->sc_dev, "couldn't enable enet_ref: %d\n", error); 226 return error; 227 } 228 229 return 0; 230 } 231 232 static void 233 enet_phy_reset(struct enet_fdt_softc *sc, const int phandle) 234 { 235 u_int msec; 236 237 sc->sc_pin_reset = fdtbus_gpio_acquire(phandle, "phy-reset-gpios", GPIO_PIN_OUTPUT); 238 if (sc->sc_pin_reset == NULL) { 239 aprint_error_dev(sc->sc_enet.sc_dev, "couldn't find phy reset gpios\n"); 240 return; 241 } 242 243 if (of_getprop_uint32(phandle, "phy-reset-duration", &msec)) 244 msec = 1; 245 246 /* Reset */ 247 fdtbus_gpio_write(sc->sc_pin_reset, 1); 248 delay(msec * 1000); 249 fdtbus_gpio_write(sc->sc_pin_reset, 0); 250 251 /* Post delay */ 252 if (of_getprop_uint32(phandle, "phy-reset-post-delay", &msec)) 253 msec = 0; 254 255 delay(msec * 1000); 256 } 257 258 static int 259 enet_phy_id(struct enet_softc *sc, const int phandle) 260 { 261 int phy_phandle; 262 bus_addr_t addr; 263 264 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 265 if (phy_phandle == -1) 266 return MII_PHY_ANY; 267 268 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 269 return MII_PHY_ANY; 270 271 return (int)addr; 272 } 273
Indexes created Fri Oct 17 09:09:57 GMT 2025