1 /* $NetBSD: at91emac.c,v 1.37 2025/10/04 04:44:19 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Embedtronics Oy 5 * All rights reserved. 6 * 7 * Based on arch/arm/ep93xx/epe.c 8 * 9 * Copyright (c) 2004 Jesse Off 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.37 2025/10/04 04:44:19 thorpej Exp $"); 36 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/ioctl.h> 41 #include <sys/kernel.h> 42 #include <sys/proc.h> 43 #include <sys/time.h> 44 #include <sys/device.h> 45 #include <uvm/uvm_extern.h> 46 47 #include <sys/bus.h> 48 #include <machine/intr.h> 49 50 #include <arm/cpufunc.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_types.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 #include <net/bpf.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #ifdef INET 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #include <netinet/if_inarp.h> 68 #endif 69 70 #include <arm/at91/at91var.h> 71 #include <arm/at91/at91emacreg.h> 72 #include <arm/at91/at91emacvar.h> 73 74 #define DEFAULT_MDCDIV 32 75 76 #ifndef EMAC_FAST 77 #define EMAC_FAST 78 #endif 79 80 #ifndef EMAC_FAST 81 #define EMAC_READ(x) \ 82 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x)) 83 #define EMAC_WRITE(x, y) \ 84 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y)) 85 #else 86 #define EMAC_READ(x) ETHREG(x) 87 #define EMAC_WRITE(x, y) ETHREG(x) = (y) 88 #endif /* ! EMAC_FAST */ 89 90 static int emac_match(device_t, cfdata_t, void *); 91 static void emac_attach(device_t, device_t, void *); 92 static void emac_init(struct emac_softc *); 93 static int emac_intr(void* arg); 94 static int emac_gctx(struct emac_softc *); 95 int emac_mii_readreg (device_t, int, int, uint16_t *); 96 int emac_mii_writereg (device_t, int, int, uint16_t); 97 void emac_statchg (struct ifnet *); 98 void emac_tick (void *); 99 static int emac_ifioctl (struct ifnet *, u_long, void *); 100 static void emac_ifstart (struct ifnet *); 101 static void emac_ifwatchdog (struct ifnet *); 102 static int emac_ifinit (struct ifnet *); 103 static void emac_ifstop (struct ifnet *, int); 104 static void emac_setaddr (struct ifnet *); 105 106 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc), 107 emac_match, emac_attach, NULL, NULL); 108 109 #ifdef EMAC_DEBUG 110 int emac_debug = EMAC_DEBUG; 111 #define DPRINTFN(n, fmt) if (emac_debug >= (n)) printf fmt 112 #else 113 #define DPRINTFN(n, fmt) 114 #endif 115 116 static int 117 emac_match(device_t parent, cfdata_t match, void *aux) 118 { 119 if (strcmp(match->cf_name, "at91emac") == 0) 120 return 2; 121 return 0; 122 } 123 124 static void 125 emac_attach(device_t parent, device_t self, void *aux) 126 { 127 struct emac_softc *sc = device_private(self); 128 struct at91bus_attach_args *sa = aux; 129 uint32_t u; 130 131 printf("\n"); 132 sc->sc_dev = self; 133 sc->sc_iot = sa->sa_iot; 134 sc->sc_pid = sa->sa_pid; 135 sc->sc_dmat = sa->sa_dmat; 136 137 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh)) 138 panic("%s: Cannot map registers", device_xname(self)); 139 140 /* enable peripheral clock */ 141 at91_peripheral_clock(sc->sc_pid, 1); 142 143 /* configure emac: */ 144 EMAC_WRITE(ETH_CTL, 0); // disable everything 145 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 146 EMAC_WRITE(ETH_RBQP, 0); // clear receive 147 EMAC_WRITE(ETH_CFG, 148 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 149 EMAC_WRITE(ETH_TCR, 0); // send nothing 150 //(void)EMAC_READ(ETH_ISR); 151 u = EMAC_READ(ETH_TSR); 152 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 153 | ETH_TSR_IDLE | ETH_TSR_RLE 154 | ETH_TSR_COL | ETH_TSR_OVR))); 155 u = EMAC_READ(ETH_RSR); 156 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 157 158 /* Fetch the Ethernet address from property if set. */ 159 if (! ether_getaddr(self, sc->sc_enaddr)) { 160 static const uint8_t hardcoded[ETHER_ADDR_LEN] = { 161 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94 162 }; 163 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN); 164 } 165 166 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr, 167 sc); 168 emac_init(sc); 169 } 170 171 static int 172 emac_gctx(struct emac_softc *sc) 173 { 174 uint32_t tsr; 175 176 tsr = EMAC_READ(ETH_TSR); 177 if (!(tsr & ETH_TSR_BNQ)) { 178 // no space left 179 return 0; 180 } 181 182 // free sent frames 183 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) { 184 int i = sc->txqi % TX_QLEN; 185 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0, 186 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE); 187 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap); 188 m_freem(sc->txq[i].m); 189 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n", 190 __FUNCTION__, i, sc->txq[i].m, sc->txqc)); 191 sc->txq[i].m = NULL; 192 sc->txqi = (i + 1) % TX_QLEN; 193 sc->txqc--; 194 } 195 196 // mark we're free 197 if (sc->tx_busy) { 198 sc->tx_busy = false; 199 /* Disable transmit-buffer-free interrupt */ 200 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/ 201 } 202 203 return 1; 204 } 205 206 static int 207 emac_intr(void *arg) 208 { 209 struct emac_softc *sc = (struct emac_softc *)arg; 210 struct ifnet * ifp = &sc->sc_ec.ec_if; 211 uint32_t imr, isr, ctl; 212 int bi; 213 214 imr = ~EMAC_READ(ETH_IMR); 215 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 216 | ETH_ISR_RBNA | ETH_ISR_ROVR))) { 217 // interrupt not enabled, can't be us 218 return 0; 219 } 220 221 isr = EMAC_READ(ETH_ISR) & imr; 222 #ifdef EMAC_DEBUG 223 uint32_t rsr = 224 #endif 225 EMAC_READ(ETH_RSR); // get receive status register 226 227 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__, 228 isr, rsr, imr)); 229 230 if (isr & ETH_ISR_RBNA) { // out of receive buffers 231 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt 232 ctl = EMAC_READ(ETH_CTL); // get current control register value 233 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 234 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit 235 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver 236 if_statinc(ifp, if_ierrors); 237 if_statinc(ifp, if_ipackets); 238 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__)); 239 } 240 if (isr & ETH_ISR_ROVR) { 241 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt 242 if_statinc(ifp, if_ierrors); 243 if_statinc(ifp, if_ipackets); 244 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__)); 245 } 246 247 if (isr & ETH_ISR_RCOM) { // packet has been received! 248 uint32_t nfo; 249 // @@@ if memory is NOT coherent, then we're in trouble @@@@ 250 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 251 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr); 252 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN, 253 sc->RDSC[sc->rxqi % RX_QLEN].Info)); 254 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) { 255 int fl; 256 struct mbuf *m; 257 258 nfo = sc->RDSC[bi].Info; 259 fl = (nfo & ETH_RDSC_I_LEN) - 4; 260 DPRINTFN(2,("## nfo=0x%08X\n", nfo)); 261 262 MGETHDR(m, M_DONTWAIT, MT_DATA); 263 if (m != NULL) MCLGET(m, M_DONTWAIT); 264 if (m != NULL && (m->m_flags & M_EXT)) { 265 bus_dmamap_sync(sc->sc_dmat, 266 sc->rxq[bi].m_dmamap, 0, 267 MCLBYTES, BUS_DMASYNC_POSTREAD); 268 bus_dmamap_unload(sc->sc_dmat, 269 sc->rxq[bi].m_dmamap); 270 m_set_rcvif(sc->rxq[bi].m, ifp); 271 sc->rxq[bi].m->m_pkthdr.len = 272 sc->rxq[bi].m->m_len = fl; 273 DPRINTFN(2,("received %u bytes packet\n", fl)); 274 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m); 275 if (mtod(m, intptr_t) & 3) { 276 m_adj(m, mtod(m, intptr_t) & 3); 277 } 278 sc->rxq[bi].m = m; 279 bus_dmamap_load(sc->sc_dmat, 280 sc->rxq[bi].m_dmamap, 281 m->m_ext.ext_buf, MCLBYTES, 282 NULL, BUS_DMA_NOWAIT); 283 bus_dmamap_sync(sc->sc_dmat, 284 sc->rxq[bi].m_dmamap, 0, 285 MCLBYTES, BUS_DMASYNC_PREREAD); 286 sc->RDSC[bi].Info = 0; 287 sc->RDSC[bi].Addr = 288 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr 289 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 290 } else { 291 /* Drop packets until we can get replacement 292 * empty mbufs for the RXDQ. 293 */ 294 m_freem(m); 295 if_statinc(ifp, if_ierrors); 296 } 297 sc->rxqi++; 298 } 299 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 300 } 301 302 if (emac_gctx(sc) > 0) 303 if_schedule_deferred_start(ifp); 304 #if 0 // reloop 305 irq = EMAC_READ(IntStsC); 306 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0) 307 goto begin; 308 #endif 309 310 return (1); 311 } 312 313 314 static void 315 emac_init(struct emac_softc *sc) 316 { 317 bus_dma_segment_t segs; 318 void *addr; 319 int rsegs, err, i; 320 struct ifnet * ifp = &sc->sc_ec.ec_if; 321 struct mii_data * const mii = &sc->sc_mii; 322 uint32_t u; 323 #if 0 324 int mdcdiv = DEFAULT_MDCDIV; 325 #endif 326 327 callout_init(&sc->emac_tick_ch, 0); 328 329 // ok... 330 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 331 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 332 EMAC_WRITE(ETH_RBQP, 0); // clear receive 333 EMAC_WRITE(ETH_CFG, 334 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 335 EMAC_WRITE(ETH_TCR, 0); // send nothing 336 // (void)EMAC_READ(ETH_ISR); 337 u = EMAC_READ(ETH_TSR); 338 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 339 | ETH_TSR_IDLE | ETH_TSR_RLE 340 | ETH_TSR_COL | ETH_TSR_OVR))); 341 u = EMAC_READ(ETH_RSR); 342 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 343 344 /* configure EMAC */ 345 EMAC_WRITE(ETH_CFG, 346 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 347 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); 348 #if 0 349 if (device_cfdata(sc->sc_dev)->cf_flags) 350 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags; 351 #endif 352 /* set ethernet address */ 353 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 354 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 355 | (sc->sc_enaddr[0])); 356 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 357 | (sc->sc_enaddr[4])); 358 EMAC_WRITE(ETH_SA2L, 0); 359 EMAC_WRITE(ETH_SA2H, 0); 360 EMAC_WRITE(ETH_SA3L, 0); 361 EMAC_WRITE(ETH_SA3H, 0); 362 EMAC_WRITE(ETH_SA4L, 0); 363 EMAC_WRITE(ETH_SA4H, 0); 364 365 /* Allocate a page of memory for receive queue descriptors */ 366 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE; 367 sc->rbqlen *= PAGE_SIZE; 368 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen)); 369 370 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0, 371 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary 372 &segs, 1, &rsegs, BUS_DMA_WAITOK); 373 if (err == 0) { 374 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__)); 375 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen, 376 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT)); 377 } 378 if (err == 0) { 379 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__)); 380 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1, 381 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK, 382 &sc->rbqpage_dmamap); 383 } 384 if (err == 0) { 385 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__)); 386 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap, 387 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK); 388 } 389 if (err != 0) { 390 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev)); 391 } 392 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr; 393 394 memset(sc->rbqpage, 0, sc->rbqlen); 395 396 /* Set up pointers to start of each queue in kernel addr space. 397 * Each descriptor queue or status queue entry uses 2 words 398 */ 399 sc->RDSC = (void*)sc->rbqpage; 400 401 /* Populate the RXQ with mbufs */ 402 sc->rxqi = 0; 403 for (i = 0; i < RX_QLEN; i++) { 404 struct mbuf *m; 405 406 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 407 PAGE_SIZE, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap); 408 if (err) 409 panic("%s: dmamap_create failed: %i\n", 410 __FUNCTION__, err); 411 412 MGETHDR(m, M_WAIT, MT_DATA); 413 MCLGET(m, M_WAIT); 414 sc->rxq[i].m = m; 415 if (mtod(m, intptr_t) & 3) { 416 m_adj(m, mtod(m, intptr_t) & 3); 417 } 418 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap, 419 m->m_ext.ext_buf, MCLBYTES, NULL, 420 BUS_DMA_WAITOK); 421 if (err) 422 panic("%s: dmamap_load failed: %i\n", 423 __FUNCTION__, err); 424 425 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr 426 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0); 427 sc->RDSC[i].Info = 0; 428 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0, 429 MCLBYTES, BUS_DMASYNC_PREREAD); 430 } 431 432 /* prepare transmit queue */ 433 for (i = 0; i < TX_QLEN; i++) { 434 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 435 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW), 436 &sc->txq[i].m_dmamap); 437 if (err) 438 panic("ARGH #1"); 439 sc->txq[i].m = NULL; 440 } 441 442 /* Program each queue's start addr, cur addr, and len registers 443 * with the physical addresses. 444 */ 445 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, 446 BUS_DMASYNC_PREREAD); 447 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr; 448 EMAC_WRITE(ETH_RBQP, (uint32_t)addr); 449 450 /* Divide HCLK by 32 for MDC clock */ 451 mii->mii_ifp = ifp; 452 mii->mii_readreg = emac_mii_readreg; 453 mii->mii_writereg = emac_mii_writereg; 454 mii->mii_statchg = emac_statchg; 455 sc->sc_ec.ec_mii = mii; 456 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 457 ether_mediastatus); 458 mii_attach((device_t )sc, mii, 0xffffffff, MII_PHY_ANY, 459 MII_OFFSET_ANY, 0); 460 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 461 462 // enable / disable interrupts 463 464 #if 0 465 // enable / disable interrupts 466 EMAC_WRITE(ETH_IDR, -1); 467 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 468 | ETH_ISR_RBNA | ETH_ISR_ROVR); 469 // (void)EMAC_READ(ETH_ISR); // why 470 471 // enable transmitter / receiver 472 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 473 | ETH_CTL_CSR | ETH_CTL_MPE); 474 #endif 475 /* 476 * We can support 802.1Q VLAN-sized frames. 477 */ 478 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 479 480 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 481 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 482 ifp->if_ioctl = emac_ifioctl; 483 ifp->if_start = emac_ifstart; 484 ifp->if_watchdog = emac_ifwatchdog; 485 ifp->if_init = emac_ifinit; 486 ifp->if_stop = emac_ifstop; 487 ifp->if_timer = 0; 488 ifp->if_softc = sc; 489 IFQ_SET_READY(&ifp->if_snd); 490 if_attach(ifp); 491 if_deferred_start_init(ifp, NULL); 492 ether_ifattach(ifp, (sc)->sc_enaddr); 493 } 494 495 int 496 emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 497 { 498 #ifndef EMAC_FAST 499 struct emac_softc *sc = device_private(self); 500 #endif 501 502 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD 503 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 504 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 505 | ETH_MAN_CODE_IEEE802_3)); 506 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) 507 ; 508 *val = EMAC_READ(ETH_MAN) & ETH_MAN_DATA; 509 510 return 0; 511 } 512 513 int 514 emac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 515 { 516 #ifndef EMAC_FAST 517 struct emac_softc *sc = device_private(self); 518 #endif 519 520 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR 521 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA) 522 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA) 523 | ETH_MAN_CODE_IEEE802_3 524 | (val & ETH_MAN_DATA))); 525 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE)) 526 ; 527 528 return 0; 529 } 530 531 void 532 emac_statchg(struct ifnet *ifp) 533 { 534 struct emac_softc *sc = ifp->if_softc; 535 uint32_t reg; 536 537 /* 538 * We must keep the MAC and the PHY in sync as 539 * to the status of full-duplex! 540 */ 541 reg = EMAC_READ(ETH_CFG); 542 if (sc->sc_mii.mii_media_active & IFM_FDX) 543 reg |= ETH_CFG_FD; 544 else 545 reg &= ~ETH_CFG_FD; 546 EMAC_WRITE(ETH_CFG, reg); 547 } 548 549 void 550 emac_tick(void *arg) 551 { 552 struct emac_softc* sc = (struct emac_softc *)arg; 553 struct ifnet * ifp = &sc->sc_ec.ec_if; 554 int s; 555 uint32_t misses; 556 557 if_statadd(ifp, if_collisions, EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL)); 558 /* These misses are ok, they will happen if the RAM/CPU can't keep up */ 559 misses = EMAC_READ(ETH_DRFC); 560 if (misses > 0) 561 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses); 562 563 s = splnet(); 564 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 565 emac_ifstart(ifp); 566 } 567 splx(s); 568 569 mii_tick(&sc->sc_mii); 570 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 571 } 572 573 574 static int 575 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 576 { 577 int s, error; 578 579 s = splnet(); 580 switch (cmd) { 581 default: 582 error = ether_ioctl(ifp, cmd, data); 583 if (error == ENETRESET) { 584 if (ifp->if_flags & IFF_RUNNING) 585 emac_setaddr(ifp); 586 error = 0; 587 } 588 } 589 splx(s); 590 return error; 591 } 592 593 static void 594 emac_ifstart(struct ifnet *ifp) 595 { 596 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 597 struct mbuf *m; 598 bus_dma_segment_t *segs; 599 int s, bi, err, nsegs; 600 601 s = splnet(); 602 start: 603 if (emac_gctx(sc) == 0) { 604 /* Enable transmit-buffer-free interrupt */ 605 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 606 sc->tx_busy = true; 607 ifp->if_timer = 10; 608 splx(s); 609 return; 610 } 611 612 ifp->if_timer = 0; 613 614 IFQ_POLL(&ifp->if_snd, m); 615 if (m == NULL) { 616 splx(s); 617 return; 618 } 619 //more: 620 bi = (sc->txqi + sc->txqc) % TX_QLEN; 621 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 622 BUS_DMA_NOWAIT)) || 623 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 || 624 sc->txq[bi].m_dmamap->dm_nsegs > 1) { 625 /* Copy entire mbuf chain to new single */ 626 struct mbuf *mn; 627 628 if (err == 0) 629 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap); 630 631 MGETHDR(mn, M_DONTWAIT, MT_DATA); 632 if (mn == NULL) goto stop; 633 if (m->m_pkthdr.len > MHLEN) { 634 MCLGET(mn, M_DONTWAIT); 635 if ((mn->m_flags & M_EXT) == 0) { 636 m_freem(mn); 637 goto stop; 638 } 639 } 640 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *)); 641 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len; 642 IFQ_DEQUEUE(&ifp->if_snd, m); 643 m_freem(m); 644 m = mn; 645 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m, 646 BUS_DMA_NOWAIT); 647 } else { 648 IFQ_DEQUEUE(&ifp->if_snd, m); 649 } 650 651 bpf_mtap(ifp, m, BPF_D_OUT); 652 653 nsegs = sc->txq[bi].m_dmamap->dm_nsegs; 654 segs = sc->txq[bi].m_dmamap->dm_segs; 655 if (nsegs > 1) { 656 panic("#### ARGH #2"); 657 } 658 659 sc->txq[bi].m = m; 660 sc->txqc++; 661 662 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr, 663 (unsigned)m->m_pkthdr.len)); 664 #ifdef DIAGNOSTIC 665 if (sc->txqc > TX_QLEN) { 666 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN); 667 } 668 #endif 669 670 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0, 671 sc->txq[bi].m_dmamap->dm_mapsize, 672 BUS_DMASYNC_PREWRITE); 673 674 EMAC_WRITE(ETH_TAR, segs->ds_addr); 675 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len); 676 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 677 goto start; 678 stop: 679 680 splx(s); 681 return; 682 } 683 684 static void 685 emac_ifwatchdog(struct ifnet *ifp) 686 { 687 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc; 688 689 if ((ifp->if_flags & IFF_RUNNING) == 0) 690 return; 691 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n", 692 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG)); 693 } 694 695 static int 696 emac_ifinit(struct ifnet *ifp) 697 { 698 struct emac_softc *sc = ifp->if_softc; 699 int s = splnet(); 700 701 callout_stop(&sc->emac_tick_ch); 702 703 // enable interrupts 704 EMAC_WRITE(ETH_IDR, -1); 705 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE 706 | ETH_ISR_RBNA | ETH_ISR_ROVR); 707 708 // enable transmitter / receiver 709 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR 710 | ETH_CTL_CSR | ETH_CTL_MPE); 711 712 mii_mediachg(&sc->sc_mii); 713 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 714 ifp->if_flags |= IFF_RUNNING; 715 splx(s); 716 return 0; 717 } 718 719 static void 720 emac_ifstop(struct ifnet *ifp, int disable) 721 { 722 // uint32_t u; 723 struct emac_softc *sc = ifp->if_softc; 724 725 #if 0 726 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything 727 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 728 // EMAC_WRITE(ETH_RBQP, 0); // clear receive 729 EMAC_WRITE(ETH_CFG, 730 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG); 731 EMAC_WRITE(ETH_TCR, 0); // send nothing 732 // (void)EMAC_READ(ETH_ISR); 733 u = EMAC_READ(ETH_TSR); 734 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ 735 | ETH_TSR_IDLE | ETH_TSR_RLE 736 | ETH_TSR_COL | ETH_TSR_OVR))); 737 u = EMAC_READ(ETH_RSR); 738 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA))); 739 #endif 740 callout_stop(&sc->emac_tick_ch); 741 742 /* Down the MII. */ 743 mii_down(&sc->sc_mii); 744 745 ifp->if_flags &= ~IFF_RUNNING; 746 ifp->if_timer = 0; 747 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE; 748 } 749 750 static void 751 emac_setaddr(struct ifnet *ifp) 752 { 753 struct emac_softc *sc = ifp->if_softc; 754 struct ethercom *ec = &sc->sc_ec; 755 struct ether_multi *enm; 756 struct ether_multistep step; 757 uint8_t ias[3][ETHER_ADDR_LEN]; 758 uint32_t h, nma = 0, hashes[2] = { 0, 0 }; 759 uint32_t ctl = EMAC_READ(ETH_CTL); 760 uint32_t cfg = EMAC_READ(ETH_CFG); 761 762 /* disable receiver temporarily */ 763 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 764 765 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF); 766 767 if (ifp->if_flags & IFF_PROMISC) { 768 cfg |= ETH_CFG_CAF; 769 } else { 770 cfg &= ~ETH_CFG_CAF; 771 } 772 773 // ETH_CFG_BIG? 774 775 ifp->if_flags &= ~IFF_ALLMULTI; 776 777 ETHER_LOCK(ec); 778 ETHER_FIRST_MULTI(step, ec, enm); 779 while (enm != NULL) { 780 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 781 /* 782 * We must listen to a range of multicast addresses. 783 * For now, just accept all multicasts, rather than 784 * trying to set only those filter bits needed to match 785 * the range. (At this time, the only use of address 786 * ranges is for IP multicast routing, for which the 787 * range is big enough to require all bits set.) 788 */ 789 cfg |= ETH_CFG_CAF; 790 hashes[0] = 0xffffffffUL; 791 hashes[1] = 0xffffffffUL; 792 ifp->if_flags |= IFF_ALLMULTI; 793 nma = 0; 794 break; 795 } 796 797 if (nma < 3) { 798 /* We can program 3 perfect address filters for mcast */ 799 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN); 800 } else { 801 /* 802 * XXX: Datasheet is not very clear here, I'm not sure 803 * if I'm doing this right. --joff 804 */ 805 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 806 807 /* Just want the 6 most-significant bits. */ 808 h = h >> 26; 809 810 hashes[ h / 32 ] |= (1 << (h % 32)); 811 cfg |= ETH_CFG_MTI; 812 } 813 ETHER_NEXT_MULTI(step, enm); 814 nma++; 815 } 816 ETHER_UNLOCK(ec); 817 818 // program... 819 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, 820 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2], 821 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5])); 822 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24) 823 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8) 824 | (sc->sc_enaddr[0])); 825 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8) 826 | (sc->sc_enaddr[4])); 827 if (nma > 1) { 828 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n", 829 __FUNCTION__, 830 ias[0][0], ias[0][1], ias[0][2], 831 ias[0][3], ias[0][4], ias[0][5])); 832 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24) 833 | (ias[0][2] << 16) | (ias[0][1] << 8) 834 | (ias[0][0])); 835 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8) 836 | (ias[0][5])); 837 } 838 if (nma > 2) { 839 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n", 840 __FUNCTION__, 841 ias[1][0], ias[1][1], ias[1][2], 842 ias[1][3], ias[1][4], ias[1][5])); 843 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24) 844 | (ias[1][2] << 16) | (ias[1][1] << 8) 845 | (ias[1][0])); 846 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8) 847 | (ias[1][5])); 848 } 849 if (nma > 3) { 850 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n", 851 __FUNCTION__, 852 ias[2][0], ias[2][1], ias[2][2], 853 ias[2][3], ias[2][4], ias[2][5])); 854 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24) 855 | (ias[2][2] << 16) | (ias[2][1] << 8) 856 | (ias[2][0])); 857 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8) 858 | (ias[2][5])); 859 } 860 EMAC_WRITE(ETH_HSH, hashes[0]); 861 EMAC_WRITE(ETH_HSL, hashes[1]); 862 EMAC_WRITE(ETH_CFG, cfg); 863 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); 864 } 865
Indexes created Sat Oct 11 14:09:46 GMT 2025