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    Searched refs:emitLoad (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64LowerHomogeneousPrologEpilog.cpp 219 static void emitLoad(MachineFunction &MF, MachineBasicBlock &MBB,
333 emitLoad(MF, MBB, MBB.end(), TII, Regs[I], Regs[I + 1], Size - I - 2,
336 emitLoad(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], Size,
470 emitLoad(MF, MBB, MBBI, *TII, Regs[I], Regs[I + 1], Size - I - 2, false);
472 emitLoad(MF, MBB, MBBI, *TII, Regs[Size - 2], Regs[Size - 1], Size, true);
AArch64FastISel.cpp 225 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
1733 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1974 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
1999 // Delete the last emitted instruction from emitLoad (SUBREG_TO_REG).
3297 unsigned ResultReg = emitLoad(VT, VT, Src);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
756 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
905 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))

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