| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| scheduler.h | 148 intel_engine_mask_t engine_mask);
153 intel_engine_mask_t engine_mask,
166 intel_engine_mask_t engine_mask);
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| execlist.c | 535 intel_engine_mask_t engine_mask)
542 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
550 intel_engine_mask_t engine_mask)
556 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp)
561 intel_engine_mask_t engine_mask)
563 reset_execlist(vgpu, engine_mask);
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| execlist.h | 187 intel_engine_mask_t engine_mask);
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| vgpu.c | 509 * @engine_mask: engines to reset for GT reset
528 * The parameter engine_mask is to specific the engines that need to be
529 * resetted. If value ALL_ENGINES is given for engine_mask, it means
531 * GPU engines. For FLR, engine_mask is ignored.
534 intel_engine_mask_t engine_mask)
538 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
541 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
542 vgpu->id, dmlr, engine_mask);
559 if (engine_mask == ALL_ENGINES || dmlr) {
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| scheduler.c | 874 intel_engine_mask_t engine_mask)
883 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
1178 * @engine_mask: engines expected to be reset
1184 intel_engine_mask_t engine_mask)
1191 intel_vgpu_clean_workloads(vgpu, engine_mask);
1192 s->ops->reset(vgpu, engine_mask);
1304 * @engine_mask: either ALL_ENGINES or target engine mask
1314 intel_engine_mask_t engine_mask,
1327 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1331 s->ops->clean(vgpu, engine_mask);
[all...] |
| gvt.h | 146 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
148 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
490 intel_engine_mask_t engine_mask);
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| handlers.c | 319 intel_engine_mask_t engine_mask = 0; local in function:gdrst_mmio_write
327 engine_mask = ALL_ENGINES;
331 engine_mask |= BIT(RCS0);
335 engine_mask |= BIT(VCS0);
339 engine_mask |= BIT(BCS0);
343 engine_mask |= BIT(VECS0);
347 engine_mask |= BIT(VCS1);
353 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
357 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_reset.c | 182 intel_engine_mask_t engine_mask,
211 intel_engine_mask_t engine_mask,
221 intel_engine_mask_t engine_mask,
257 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
317 intel_engine_mask_t engine_mask,
330 if (engine_mask == ALL_ENGINES) {
336 for_each_engine_masked(engine, gt, engine_mask, tmp) {
448 intel_engine_mask_t engine_mask,
466 if (engine_mask == ALL_ENGINES) {
470 for_each_engine_masked(engine, gt, engine_mask, tmp)
[all...] |
| intel_reset.h | 29 intel_engine_mask_t engine_mask,
55 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
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| intel_gt.h | 52 intel_engine_mask_t engine_mask);
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| intel_engine_cs.c | 436 const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask; local in function:intel_engines_init_mmio
441 WARN_ON(engine_mask == 0);
442 WARN_ON(engine_mask &
464 if (WARN_ON(mask != engine_mask))
465 device_info->engine_mask = mask;
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| intel_gt.c | 159 intel_engine_mask_t engine_mask)
196 for_each_engine_masked(engine, gt, engine_mask, id)
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_pci.c | 174 .engine_mask = BIT(RCS0), \
192 .engine_mask = BIT(RCS0), \
227 .engine_mask = BIT(RCS0), \
313 .engine_mask = BIT(RCS0), \
344 .engine_mask = BIT(RCS0) | BIT(VCS0),
354 .engine_mask = BIT(RCS0) | BIT(VCS0),
362 .engine_mask = BIT(RCS0) | BIT(VCS0), \
390 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
439 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
506 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0)
[all...] |
| intel_device_info.h | 159 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ member in struct:intel_device_info
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| intel_device_info.c | 95 drm_printf(p, "engines: %x\n", info->engine_mask);
1091 info->engine_mask &= ~BIT(_VCS(i));
1115 info->engine_mask &= ~BIT(_VECS(i));
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| i915_drv.h | 1372 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1651 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1656 (INTEL_INFO(dev_priv)->engine_mask & \
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| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| mock_gem_device.c | 185 mkwrite_device_info(i915)->engine_mask = BIT(0);
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| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_execbuffer.c | 2259 return hweight64(INTEL_INFO(i915)->engine_mask &
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