| /src/sys/arch/sun3/dev/ |
| sebuf.c | 88 struct ie_regs *ereg; local in function:sebuf_match
116 ereg = bus_tmapin(ca->ca_bustype, pa);
118 ereg->ie_csr = 0x0FFF;
119 x = peek_word((void *)(&ereg->ie_csr));
120 bus_tmapout(ereg);
|
| /src/sys/arch/mipsco/mipsco/ |
| mips_3x30.c | 171 uint32_t ereg; local in function:pizazz_level5_intr
173 ereg = *(uint32_t *)RAMBO_ERREG;
176 printf("parity error: %p mask: 0x%x\n", (void *)ereg, ereg & 0xf);
|
| /src/sys/arch/arm/iomd/ |
| vidc20config.c | 275 /* vidcvideo_write ( VIDC_EREG, vidc->ereg ); */
441 int ereg; local in function:vidcvideo_setmode
510 ereg = 1<<12;
512 ereg |= 1<<16;
514 ereg |= 1<<18;
515 vidcvideo_write(VIDC_EREG, ereg);
742 int ereg; local in function:vidcvideo_blank
744 ereg = 1<<12;
746 ereg |= 1<<16;
748 ereg |= 1<<18
[all...] |
| vidc.h | 175 int ereg; member in struct:vidc_state
|
| /src/sys/dev/i2c/ |
| axp809.c | 66 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \
70 .c_enable_reg = AXP_##ereg##_REG, .c_enable_mask = (emask), \
73 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \
77 .c_enable_reg = AXP_##ereg##_REG, .c_enable_mask = (emask), \
|
| axppmic.c | 136 #define AXP_CTRL(name, min, max, step, ereg, emask, vreg, vmask) \
140 .c_enable_reg = (ereg), .c_enable_mask = (emask), \
144 #define AXP_CTRL2(name, min, max, step1, step1cnt, step2, step2cnt, ereg, emask, vreg, vmask) \
148 .c_enable_reg = (ereg), .c_enable_mask = (emask), \
152 #define AXP_CTRL2_RANGE(name, min, max, step1, step1cnt, step2start, step2, step2cnt, ereg, emask, vreg, vmask) \
157 .c_enable_reg = (ereg), .c_enable_mask = (emask), \
161 #define AXP_CTRL_IO(name, min, max, step, ereg, emask, eval, dval, vreg, vmask) \
165 .c_enable_reg = (ereg), .c_enable_mask = (emask), \
169 #define AXP_CTRL_SW(name, ereg, emask) \
171 .c_enable_reg = (ereg), .c_enable_mask = (emask),
[all...] |
