| /src/sys/arch/arm/s3c2xx0/ |
| sscom_s3c2440.c | 180 s3c24x0_intr_establish(s3c2440_uart_config[unit].err_int,
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| sscom_var.h | 201 char tx_int, rx_int, err_int; member in struct:sscom_uart_info
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| sscom_s3c2410.c | 159 s3c24x0_intr_establish(s3c2410_uart_config[unit].err_int,
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| sscom_s3c2800.c | 147 s3c2800_intr_establish(s3c2800_uart_config[unit].err_int,
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_fifo_underrun.c | 151 u32 err_int = I915_READ(GEN7_ERR_INT); local in function:ivb_check_fifo_underruns
155 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gpu_error.h | 127 u32 err_int; /* gen7 */ member in struct:intel_gt_coredump
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| i915_irq.c | 1772 u32 err_int = I915_READ(GEN7_ERR_INT); local in function:ivb_err_int_handler
1775 if (err_int & ERR_INT_POISON)
1779 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1782 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1790 I915_WRITE(GEN7_ERR_INT, err_int);
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| i915_gpu_error.c | 707 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
1576 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
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| /src/sys/dev/marvell/ |
| mvxpsec.c | 100 int err_int; member in struct:__anon1cd4d9e20108
102 { .err_int = ARMADAXP_IRQ_CESA0_ERR, }, /* unit 0 */
103 { .err_int = ARMADAXP_IRQ_CESA1_ERR, }, /* unit 1 */
106 mvxpsec_config[device_unit((sc)->sc_dev)].err_int
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