| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| vega10_smumgr.h | 48 bool enable, uint32_t feature_mask);
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| vega12_smumgr.h | 54 bool enable, uint64_t feature_mask);
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| vega20_smumgr.h | 53 bool enable, uint64_t feature_mask);
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| amdgpu_vega12_smumgr.c | 126 bool enable, uint64_t feature_mask)
130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
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| amdgpu_vega20_smumgr.c | 313 bool enable, uint64_t feature_mask)
318 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
319 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
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| amdgpu_vega10_smumgr.c | 112 bool enable, uint32_t feature_mask)
126 msg, feature_mask);
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| amdgpu_smu7_smumgr.c | 590 (hwmgr->feature_mask & PP_AVFS_MASK))
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_hwmgr.c | 112 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
123 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
128 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
133 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
141 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
146 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
154 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
159 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
180 hwmgr->feature_mask &= ~PP_GFXOFF_MASK
[all...] |
| amdgpu_vega10_hwmgr.c | 125 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
127 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
129 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
131 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
134 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
136 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
143 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
146 hwmgr->feature_mask & PP_ULV_MASK ? true : false;
149 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
158 hwmgr->feature_mask & PP_AVFS_MASK ? true : false
2843 uint32_t i, feature_mask = 0; local in function:vega10_stop_dpm
2882 uint32_t i, feature_mask = 0; local in function:vega10_start_dpm
5343 uint32_t feature_mask = 0; local in function:vega10_disable_power_features_for_compute_performance
[all...] |
| amdgpu_vega20_hwmgr.c | 107 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
110 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
113 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
116 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
119 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
122 if (!(hwmgr->feature_mask & PP_ULV_MASK))
125 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
1803 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1811 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1821 (feature_mask & FEATURE_DPM_UCLK_MASK))
[all...] |
| amdgpu_smu7_clockpowergating.c | 175 if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))
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| amdgpu_smu7_hwmgr.c | 196 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
1107 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1579 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1580 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1581 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1589 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1673 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
2234 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
3954 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| smu_v12_0.h | 81 uint32_t *feature_mask, uint32_t num);
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| smu_v11_0.h | 196 uint32_t *feature_mask, uint32_t num);
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| amdgpu_smu.h | 425 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
523 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
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| hwmgr.h | 791 uint32_t feature_mask; member in struct:pp_hwmgr
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v12_0.c | 331 uint32_t *feature_mask, uint32_t num)
336 if (!feature_mask || num < 2)
353 feature_mask[0] = feature_mask_low;
354 feature_mask[1] = feature_mask_high;
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| amdgpu_navi10_ppt.c | 52 #define FEATURE_MASK(feature) (1ULL << feature)
54 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
55 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
56 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
57 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
58 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
59 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
60 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
61 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
336 uint32_t *feature_mask, uint32_t num
1197 uint32_t feature_mask[2]; local in function:navi10_is_dpm_running
[all...] |
| amdgpu_smu_v11_0.c | 838 uint32_t feature_mask[2]; local in function:smu_v11_0_set_allowed_mask
844 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
847 feature_mask[1]);
852 feature_mask[0]);
862 uint32_t *feature_mask, uint32_t num)
868 if (!feature_mask || num < 2)
886 feature_mask[0] = feature_mask_low;
887 feature_mask[1] = feature_mask_high;
889 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
900 uint32_t feature_mask[2] local in function:smu_v11_0_system_features_control
[all...] |
| amdgpu_smu.c | 77 uint32_t feature_mask[2] = { 0 }; local in function:smu_sys_get_pp_feature_mask
85 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
90 feature_mask[1], feature_mask[0]);
116 uint64_t feature_mask,
126 feature_low = (feature_mask >> 0 ) & 0xffffffff;
127 feature_high = (feature_mask >> 32) & 0xffffffff;
152 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
155 (unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
164 uint32_t feature_mask[2] = { 0 } local in function:smu_sys_set_pp_feature_mask
[all...] |
| smu_internal.h | 161 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
162 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
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| amdgpu_arcturus_ppt.c | 360 uint32_t *feature_mask, uint32_t num)
366 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
742 uint32_t feature_mask)
751 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
766 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
781 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1960 uint32_t feature_mask[2]; local in function:arcturus_is_dpm_running
1962 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1965 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1966 ((uint64_t)feature_mask[1] << 32))
[all...] |
| amdgpu_vega20_ppt.c | 600 #define FEATURE_MASK(feature) (1ULL << feature)
603 uint32_t *feature_mask, uint32_t num)
608 memset(feature_mask, 0, sizeof(uint32_t) * num);
610 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
611 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
612 | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
613 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
614 | FEATURE_MASK(FEATURE_DPM_UVD_BIT)
615 | FEATURE_MASK(FEATURE_DPM_VCE_BIT
2849 uint32_t feature_mask[2]; local in function:vega20_is_dpm_running
[all...] |
| amdgpu_amd_powerplay.c | 61 hwmgr->feature_mask = adev->pm.pp_feature;
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| /src/sys/external/bsd/ena-com/ |
| ena_com.c | 892 u32 feature_mask = 1 << feature_id; local in function:ena_com_check_supported_feature_id
896 !(ena_dev->supported_features & feature_mask))
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