| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| DevelopmentModeInlineAdvisor.cpp | 68 static cl::opt<std::string> TFFeedPrefix("ml-inliner-trained-model-feed-prefix",
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| /src/external/lgpl3/gmp/dist/mpn/mips32/ |
| mul_1.asm | 43 C feed-in phase 0
46 C feed-in phase 1
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| addmul_1.asm | 43 C feed-in phase 0
46 C feed-in phase 1
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| submul_1.asm | 43 C feed-in phase 0
46 C feed-in phase 1
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| /src/external/lgpl3/gmp/dist/mpn/mips64/hilo/ |
| mul_1.asm | 43 C feed-in phase 0
46 C feed-in phase 1
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| addmul_1.asm | 43 C feed-in phase 0
46 C feed-in phase 1
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| submul_1.asm | 43 C feed-in phase 0
46 C feed-in phase 1
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| /src/external/ibm-public/postfix/dist/src/oqmgr/ |
| qmgr.c | 534 int feed = 0; local
573 if ((feed = qmgr_active_feed(qmgr_scans[last_scan_idx], path)) != 0)
596 if (feed != 0 && last_scan_idx == QMGR_SCAN_IDX_INCOMING)
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| /src/external/ibm-public/postfix/dist/src/qmgr/ |
| qmgr.c | 610 int feed = 0; local
647 if ((feed = qmgr_active_feed(qmgr_scans[last_scan_idx], path)) != 0)
669 if (feed != 0 && last_scan_idx == QMGR_SCAN_IDX_INCOMING)
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| /src/sys/arch/evbarm/tsarm/ |
| tsarm_machdep.c | 288 uint32_t feed, ctrl; local
290 feed = TS7XXX_IO16_VBASE + TS7XXX_WDOGFEED;
299 : "r" (feed), "r" (ctrl)
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| /src/external/lgpl3/gmp/dist/mpn/arm/v7a/cora15/neon/ |
| aorsorrlshC_n.asm | 43 C * Consider using 4-way feed-in code.
74 vmov.i8 d0, #0 C could feed carry through here
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| /src/external/lgpl3/gmp/dist/mpn/powerpc64/mode64/ |
| mul_1.asm | 44 C * Optimize feed-in code, for speed and size.
45 C * Clean up r12/r7 usage in feed-in code.
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| /src/external/lgpl3/gmp/dist/mpn/arm/v6/ |
| addmul_1.asm | 43 C * Micro-optimise feed-in code.
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| mul_1.asm | 43 C * Micro-optimise feed-in code.
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| submul_1.asm | 47 C * Micro-optimise feed-in code.
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| /src/external/lgpl3/gmp/dist/mpn/x86_64/ |
| bdiv_dbm1c.asm | 44 C * Optimise feed-in code.
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| /src/external/lgpl3/gmp/dist/mpn/s390_64/ |
| lshift.asm | 45 C * Consider using the same feed-in code for 1 <= n <= 3 as for n mod 4,
46 C similarly to the x86_64 sqr_basecase feed-in.
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| copyd.asm | 45 C * Could we use some EX trick, modifying lmg/stmg, for the feed-in code?
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| /src/external/lgpl3/gmp/dist/mpn/x86/k7/ |
| addlsh1_n.asm | 38 C cannot feed carry between operations there.
60 C cannot do rsblsh1_n since we feed carry from the shift blocks to the
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| mul_1.asm | 49 C * Improve feed-in and wind-down code. We beat the old code for all n != 1,
51 C * The feed-in code for mul_1c is crude.
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| aorsmul_1.asm | 49 C * Improve feed-in and wind-down code. We beat the old code for all n != 1,
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| /src/external/lgpl3/gmp/dist/mpn/arm64/ |
| aorsmul_1.asm | 44 C * We could separate feed-in into 4 blocks, one for each residue (mod 4).
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| lshift.asm | 39 C * The feed-in code used 1 ldr for odd sized and 2 ldr for even sizes. These
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| lshiftc.asm | 39 C * The feed-in code used 1 ldr for odd sized and 2 ldr for even sizes. These
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| rshift.asm | 39 C * The feed-in code used 1 ldr for odd sized and 2 ldr for even sizes. These
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