/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
amdgpu_bios_parser_helper.c | 59 #define FN(reg_name, field_name) \ 60 ATOM_ ## field_name ## _SHIFT, ATOM_ ## field_name
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/ |
amdgpu_hw_factory_dcn20.c | 67 #define SF_HPD(reg_name, field_name, post_fix)\ 68 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 74 #define SF(reg_name, field_name, post_fix)\ 75 .field_name = reg_name ## __ ## field_name ## post_fix 107 #define SF_DDC(reg_name, field_name, post_fix)\ 108 .field_name = reg_name ## __ ## field_name ## post_fix 161 #define SF_GENERIC(reg_name, field_name, post_fix) [all...] |
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/ |
amdgpu_hw_factory_dcn21.c | 65 #define SF_HPD(reg_name, field_name, post_fix)\ 66 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 72 #define SF(reg_name, field_name, post_fix)\ 73 .field_name = reg_name ## __ ## field_name ## post_fix 104 #define SF_DDC(reg_name, field_name, post_fix)\ 105 .field_name = reg_name ## __ ## field_name ## post_fix 144 #define SF_GENERIC(reg_name, field_name, post_fix) [all...] |
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/ |
amdgpu_hw_factory_dce120.c | 51 #define SF_HPD(reg_name, field_name, post_fix)\ 52 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 55 #define SF_HPD(reg_name, field_name, post_fix)\ 56 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 101 #define SF_DDC(reg_name, field_name, post_fix)\ 102 .field_name = reg_name ## __ ## field_name ## post_fix
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/ |
amdgpu_hw_factory_dcn10.c | 52 #define SF_HPD(reg_name, field_name, post_fix)\ 53 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix 97 #define SF_DDC(reg_name, field_name, post_fix)\ 98 .field_name = reg_name ## __ ## field_name ## post_fix 133 #define SF_GENERIC(reg_name, field_name, post_fix)\ 134 .field_name = reg_name ## __ ## field_name ## post_fix
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
dcn20_dccg.h | 46 #define DCCG_SF(reg_name, field_name, post_fix)\ 47 .field_name = reg_name ## __ ## field_name ## post_fix 49 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ 50 .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
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amdgpu_dcn20_vmid.c | 43 #define FN(reg_name, field_name) \ 44 vmid->shifts->field_name, vmid->masks->field_name
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amdgpu_dcn20_dccg.c | 44 #define FN(reg_name, field_name) \ 45 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
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dcn20_vmid.h | 43 #define SF(reg_name, field_name, post_fix)\ 44 .field_name = reg_name ## __ ## field_name ## post_fix
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dcn20_opp.h | 35 #define OPP_SF(reg_name, field_name, post_fix)\ 36 .field_name = reg_name ## __ ## field_name ## post_fix
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amdgpu_dcn20_hubbub.c | 43 #define FN(reg_name, field_name) \ 44 hubbub1->shifts->field_name, hubbub1->masks->field_name 53 #define FN(reg_name, field_name) \ 54 hubbub1->shifts->field_name, hubbub1->masks->field_name
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/ |
amdgpu_hw_factory_dce110.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ 48 .field_name = reg_name ## __ ## field_name ## post_fix 88 #define SF_DDC(reg_name, field_name, post_fix)\ 89 .field_name = reg_name ## __ ## field_name ## post_fix
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
amdgpu_dcn10_ipp.c | 41 #define FN(reg_name, field_name) \ 42 ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
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dcn10_dwb.c | 46 #define FN(reg_name, field_name) \ 47 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
amdgpu_dcn21_hwseq.c | 50 #define FN(reg_name, field_name) \ 51 hws->shifts->field_name, hws->masks->field_name
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
amdgpu_hw_generic.c | 44 #define FN(reg_name, field_name) \ 45 generic->shifts->field_name, generic->masks->field_name
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amdgpu_hw_hpd.c | 44 #define FN(reg_name, field_name) \ 45 hpd->shifts->field_name, hpd->masks->field_name
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amdgpu_hw_ddc.c | 46 #define FN(reg_name, field_name) \ 47 ddc->shifts->field_name, ddc->masks->field_name
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amdgpu_hw_gpio.c | 39 #define FN(reg_name, field_name) \ 40 gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/ |
amdgpu_hw_factory_dce80.c | 88 #define SF_DDC(reg_name, field_name, post_fix)\ 89 .field_name = reg_name ## __ ## field_name ## post_fix
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
amdgpu_dce_hwseq.c | 42 #define FN(reg_name, field_name) \ 43 hws->shifts->field_name, hws->masks->field_name
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dce_audio.h | 46 #define SF(reg_name, field_name, post_fix)\ 47 .field_name = reg_name ## __ ## field_name ## post_fix
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amdgpu_dce_ipp.c | 41 #define FN(reg_name, field_name) \ 42 ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
amdgpu_dce120_hw_sequencer.c | 51 #define FN(reg_name, field_name) \ 52 hws->shifts->field_name, hws->masks->field_name
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
clk_mgr_internal.h | 106 #define CLK_SF(reg_name, field_name, post_fix)\ 107 .field_name = reg_name ## __ ## field_name ## post_fix
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