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    Searched refs:findRegisterDefOperandIdx (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostSelectOptimize.cpp 144 int DeadNZCVIdx = II.findRegisterDefOperandIdx(AArch64::NZCV);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstr.h 1387 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1395 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1403 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1437 int findRegisterDefOperandIdx(Register Reg,
1441 /// Wrapper for findRegisterDefOperandIdx, it returns
1447 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineCombiner.cpp 200 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
209 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
253 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
EarlyIfConversion.cpp 598 int TIdx = TDef->findRegisterDefOperandIdx(TReg);
599 int FIdx = FDef->findRegisterDefOperandIdx(FReg);
AggressiveAntiDepBreaker.cpp 698 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
ModuloSchedule.cpp 1663 assert(Def->findRegisterDefOperandIdx(MI.getOperand(1).getReg()) != -1);
1889 unsigned OpIdx = MI->findRegisterDefOperandIdx(Reg);
TwoAddressInstructionPass.cpp 1241 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
MachineInstr.cpp 1036 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1041 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
RegisterCoalescer.cpp 834 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 559 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
587 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
1442 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true);
1776 if (MI.findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
4582 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true);
6184 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.cpp 212 return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1;
SIInstrInfo.cpp 6120 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) !=
6802 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLowOverheadLoops.cpp 88 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1;
ARMBaseInstrInfo.cpp 1705 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
4108 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 4233 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);

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