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    Searched refs:findRegisterUseOperandIdx (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineCombiner.cpp 201 int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
210 InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
254 UseMO->findRegisterUseOperandIdx(MO.getReg()));
StackSlotColoring.cpp 464 if (NextMI->findRegisterUseOperandIdx(LoadReg, true, nullptr) != -1) {
FixupStatepointCallerSaved.cpp 119 int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI);
PeepholeOptimizer.cpp 1512 unsigned Idx = MI.findRegisterUseOperandIdx(Reg);
TwoAddressInstructionPass.cpp 1242 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
MachineInstr.cpp 989 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
992 int MachineInstr::findRegisterUseOperandIdx(
RegisterCoalescer.cpp 709 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg(), true);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstr.h 1357 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1378 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1413 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1416 /// Wrapper for findRegisterUseOperandIdx, it returns
1420 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVETPAndVPTOptimisationsPass.cpp 637 if (Iter->findRegisterUseOperandIdx(Reg) != -1) {
642 if (Iter->findRegisterUseOperandIdx(VPNOTResult) == -1)
696 Iter->findRegisterUseOperandIdx(VCCRValue) != -1) {
ARMLowOverheadLoops.cpp 92 return MI.findRegisterUseOperandIdx(ARM::VPR) != -1;
ARMBaseInstrInfo.cpp 4132 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
5248 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI);
5922 int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMaskingPreRA.cpp 421 int Idx = SingleExecUser->findRegisterUseOperandIdx(SavedExec);
SIPreEmitPeephole.cpp 216 MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI));
SIWholeQuadMode.cpp 1453 int Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC);
1456 Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC);
R600InstrInfo.cpp 208 return MI.findRegisterUseOperandIdx(R600::AR_X, false, &RI) != -1;
SIInstrInfo.cpp 6770 if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCPreEmitPeephole.cpp 155 int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI);
PPCInstrInfo.cpp 3151 int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
3351 EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 652 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 612 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 1548 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
1563 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 4244 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);

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