| /src/sys/arch/sparc64/include/ |
| userret.h | 85 if (!(tf->tf_tstate & TSTATE_PRIV) && fplwp != l)
|
| cpu.h | 279 #define fplwp CURCPU_INT()->ci_fplwp macro
|
| /src/sys/arch/sparc/sparc/ |
| vm_machdep.c | 227 if (cpi->fplwp != l1)
228 panic("FPU(%d): fplwp %p",
229 cpi->ci_cpuid, cpi->fplwp);
230 if (l1 == cpuinfo.fplwp)
303 if (cpi->fplwp != l)
304 panic("FPU(%d): fplwp %p",
305 cpi->ci_cpuid, cpi->fplwp);
306 if (l == cpuinfo.fplwp)
312 cpi->fplwp = NULL;
|
| trap.c | 316 if (cpuinfo.fplwp != l)
318 l, cpuinfo.fplwp);
321 cpuinfo.fplwp = NULL;
447 if (cpuinfo.fplwp != l) {
451 if (cpuinfo.fplwp != NULL) {
453 savefpstate(cpuinfo.fplwp->l_md.md_fpstate);
454 cpuinfo.fplwp->l_md.md_fpu = NULL;
469 cpi->fplwp = NULL;
474 cpuinfo.fplwp = l;
579 if (l != cpuinfo.fplwp)
[all...] |
| core_machdep.c | 96 if (l == cpuinfo.fplwp)
|
| syscall.c | 184 if (cpuinfo.fplwp != l)
186 l, cpuinfo.fplwp);
189 cpuinfo.fplwp = NULL;
|
| emul.c | 304 if (op.bits.fl && l != cpuinfo.fplwp)
|
| machdep.c | 372 if (cpi->fplwp != l)
373 panic("FPU(%d): fplwp %p",
374 cpi->ci_cpuid, cpi->fplwp);
375 if (l == cpuinfo.fplwp)
381 cpi->fplwp = NULL;
|
| cpu.c | 2301 "CPU#", "CPUINFO", "FLAGS", "CURLWP", "CURPROC", "FPLWP", "CPCB");
2309 ci->fplwp,
|
| /src/sys/arch/sparc/include/ |
| userret.h | 91 if ((tf->tf_psr & PSR_EF) != 0 && cpuinfo.fplwp != l)
|
| cpu.h | 243 struct lwp *fplwp; /* FPU owner */ member in struct:cpu_info
|
| /src/sys/arch/sparc64/sparc64/ |
| vm_machdep.c | 281 struct lwp *l = fplwp;
291 fplwp = NULL;
300 if (l == fplwp) {
333 if (l == fplwp)
|
| trap.c | 542 if (fplwp != newfplwp) {
544 if (fplwp != NULL) {
546 KASSERT(fplwp->l_md.md_fpstate != NULL);
547 savefpstate(fplwp->l_md.md_fpstate);
548 fplwp = NULL;
553 fplwp = newfplwp;
554 loadfpstate(fplwp->l_md.md_fpstate);
556 fplwp = NULL;
687 if (fplwp != l) { /* we do not have it */
691 if (fplwp != NULL) { /* someone else had it *
[all...] |
| db_interface.c | 220 if (fplwp) {
221 savefpstate(fplwp->l_md.md_fpstate);
222 DDB_REGS->db_fpstate = *fplwp->l_md.md_fpstate;
223 loadfpstate(fplwp->l_md.md_fpstate);
269 if (fplwp) {
270 *fplwp->l_md.md_fpstate = DDB_REGS->db_fpstate;
271 loadfpstate(fplwp->l_md.md_fpstate);
998 "fplwp 0x%08lx\n", ci->ci_index, (u_long)ci->ci_self,
|
| mp_subr.S | 341 sethi %hi(FPLWP), %g1
342 LDPTR [%g1 + %lo(FPLWP)], %g3
344 bne,pn CCCR, 7f ! skip if fplwp has changed
396 STPTR %g0, [%g1 + %lo(FPLWP)] ! fplwp = NULL
427 set FPLWP, %g1
428 CASPTRA [%g1] ASI_N, %g2, %g0 ! fplwp = NULL if fplwp == %g2
|
| emul.c | 295 if (op.bits.fl && l != fplwp)
359 fplwp = l;
|
| sunos32_machdep.c | 141 if (l == fplwp) {
143 fplwp = NULL;
|
| /src/common/lib/libc/arch/sparc64/string/ |
| memset.S | 141 * The last owner of the FPU registers is fplwp, and
142 * fplwp->l_md.md_fpstate is the current fpstate. If that's not
151 * fplwp at curlwp (or lwp0) and enable the FPU.
159 * pointer to curlwp->p_md.md_fpstate, clear our fplwp, and disable
|
| memcpy.S | 493 * The last owner of the FPU registers is fplwp, and
494 * fplwp->l_md.md_fpstate is the current fpstate. If that's not
503 * fplwp at curlwp (or lwp0) and enable the FPU.
511 * pointer to curlwp->p_md.md_fpstate, clear our fplwp, and disable
522 * %l1 fplwp (hi bits only)
523 * %l2 orig fplwp
|
