| /src/external/gpl3/gdb/dist/sim/frv/ |
| sem.c | 1 /* Simulator instruction semantics for frvbf.
25 #define WANT_CPU frvbf
49 SEM_FN_NAME (frvbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
76 SEM_FN_NAME (frvbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
97 SEM_FN_NAME (frvbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
118 SEM_FN_NAME (frvbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
148 SEM_FN_NAME (frvbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
172 SEM_FN_NAME (frvbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
203 SEM_FN_NAME (frvbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
224 SEM_FN_NAME (frvbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg
[all...] |
| pipeline.c | 23 #define WANT_CPU frvbf
|
| local.mk | 94 -cpu frvbf
110 $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
|
| options.c | 23 #define WANT_CPU frvbf
|
| cpu.c | 1 /* Misc. support for CPU family frvbf.
25 #define WANT_CPU frvbf
|
| traps.c | 23 #define WANT_CPU frvbf
|
| interrupts.c | 23 #define WANT_CPU frvbf
|
| memory.c | 23 #define WANT_CPU frvbf
|
| cache.c | 23 #define WANT_CPU frvbf
|
| decode.c | 1 /* Simulator instruction decoder for frvbf.
25 #define WANT_CPU frvbf
|
| model.c | 1 /* Simulator model support for frvbf.
25 #define WANT_CPU frvbf
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/frv/ |
| sem.c | 1 /* Simulator instruction semantics for frvbf.
25 #define WANT_CPU frvbf
49 SEM_FN_NAME (frvbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
76 SEM_FN_NAME (frvbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
97 SEM_FN_NAME (frvbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
118 SEM_FN_NAME (frvbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
148 SEM_FN_NAME (frvbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
172 SEM_FN_NAME (frvbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
203 SEM_FN_NAME (frvbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
224 SEM_FN_NAME (frvbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg
[all...] |
| pipeline.c | 23 #define WANT_CPU frvbf
|
| local.mk | 94 -cpu frvbf
110 $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
|
| options.c | 23 #define WANT_CPU frvbf
|
| cpu.c | 1 /* Misc. support for CPU family frvbf.
25 #define WANT_CPU frvbf
|
| traps.c | 23 #define WANT_CPU frvbf
|
| interrupts.c | 23 #define WANT_CPU frvbf
|
| memory.c | 23 #define WANT_CPU frvbf
|
| cache.c | 23 #define WANT_CPU frvbf
|
| decode.c | 1 /* Simulator instruction decoder for frvbf.
25 #define WANT_CPU frvbf
|
| model.c | 1 /* Simulator model support for frvbf.
25 #define WANT_CPU frvbf
[all...] |
