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    Searched refs:gcp (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/amiga/dev/
grf_cv.c 483 struct grf_cv_softc *gcp; local in function:grfcvattach
492 gcp = &congrf;
493 gp = &gcp->gcs_sc;
497 gcp = device_private(self);
498 gp = &gcp->gcs_sc;
510 (char *) &gcp->gcs_isr - (char *) &gp->g_display);
513 gcp->gcs_isr.isr_ipl = CV_INT_NUM;
514 gcp->gcs_isr.isr_intr = cvintr;
515 gcp->gcs_isr.isr_arg = (void *)gp;
518 add_isr(&gcp->gcs_isr)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display_types.h 1018 u32 gcp; member in struct:intel_crtc_state::__anonde7c4d451108
intel_hdmi.c 927 * Determine if default_phase=1 can be indicated in the GCP infoframe.
990 I915_WRITE(reg, crtc_state->infoframes.gcp);
1015 crtc_state->infoframes.gcp = I915_READ(reg);
1032 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1037 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
intel_display.c 12869 DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp);
13711 PIPE_CONF_CHECK_X(infoframes.gcp);

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