| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_cs.c | 525 struct amdgpu_bo *gds; local in function:amdgpu_cs_parser_bos
625 gds = p->bo_list->gds_obj;
638 if (gds) {
639 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
640 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
|
| amdgpu_kms.c | 596 gds_info.compute_partition_size = adev->gds.gds_size;
597 gds_info.gds_total_size = adev->gds.gds_size;
598 gds_info.gws_per_compute_partition = adev->gds.gws_size;
599 gds_info.oa_per_compute_partition = adev->gds.oa_size;
|
| amdgpu_gfx_v9_0.c | 167 /* GDS*/
767 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
1839 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
2430 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
2445 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4007 /* GDS Base */
4012 /* GDS Size */
4164 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
4170 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size)
[all...] |
| amdgpu_amdkfd.c | 563 return adev->gds.gws_size;
|
| amdgpu_ttm.c | 129 /* On-chip GDS memory*/
1254 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1882 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
2017 adev->gds.gds_size);
2019 DRM_ERROR("Failed initializing GDS heap.\n");
2024 adev->gds.gws_size);
2031 adev->gds.oa_size);
|
| amdgpu_gfx_v10_0.c | 278 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
1622 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1637 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3951 /* GDS Base */
3956 /* GDS Size */
4454 * between ME and GDS, leading to a hw deadlock, because ME generates
4455 * different wave IDs than the GDS expects. This situation happens
4456 * randomly when at least 5 compute pipes use GDS ordered append.
4461 * GDS to 0 for this ring (me/pipe)
[all...] |
| amdgpu.h | 924 /* GDS */
925 struct amdgpu_gds gds; member in struct:amdgpu_device
|
| amdgpu_gfx_v7_0.c | 1891 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1906 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2306 * between ME and GDS, leading to a hw deadlock, because ME generates
2307 * different wave IDs than the GDS expects. This situation happens
2308 * randomly when at least 5 compute pipes use GDS ordered append.
2313 * GDS to 0 for this ring (me/pipe).
2318 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
3329 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
4104 /* GDS Base */
4112 /* GDS Size *
[all...] |
| amdgpu_gfx_v8_0.c | 727 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
1323 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
3717 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
3732 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4384 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
5180 /* GDS Base */
5188 /* GDS Size */
6128 * between ME and GDS, leading to a hw deadlock, because ME generates
6129 * different wave IDs than the GDS expects. This situation happen
[all...] |
