1 /* $NetBSD: if_gem_pci.c,v 1.57 2025/10/04 19:18:41 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * PCI bindings for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: if_gem_pci.c,v 1.57 2025/10/04 19:18:41 thorpej Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/socket.h> 43 #include <sys/errno.h> 44 #include <sys/device.h> 45 #include <sys/kmem.h> 46 47 #include <machine/endian.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_ether.h> 53 54 #include <net/bpf.h> 55 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 #include <dev/mii/mii_bitbang.h> 62 63 #include <dev/ic/gemreg.h> 64 #include <dev/ic/gemvar.h> 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcidevs.h> 69 #include <prop/proplib.h> 70 71 struct gem_pci_softc { 72 struct gem_softc gsc_gem; /* GEM device */ 73 void *gsc_ih; 74 pci_chipset_tag_t gsc_pc; 75 pci_intr_handle_t gsc_handle; 76 }; 77 78 static bool gem_pci_estintr(struct gem_pci_softc *); 79 static bool gem_pci_suspend(device_t, const pmf_qual_t *); 80 static bool gem_pci_resume(device_t, const pmf_qual_t *); 81 static int gem_pci_detach(device_t, int); 82 83 int gem_pci_match(device_t, cfdata_t, void *); 84 void gem_pci_attach(device_t, device_t, void *); 85 86 CFATTACH_DECL3_NEW(gem_pci, sizeof(struct gem_pci_softc), 87 gem_pci_match, gem_pci_attach, gem_pci_detach, NULL, NULL, NULL, 88 DVF_DETACH_SHUTDOWN); 89 90 #define SUNW(p) PCI_ID_CODE(PCI_VENDOR_SUN, (p)) 91 #define AAPL(p) PCI_ID_CODE(PCI_VENDOR_APPLE, (p)) 92 93 static const struct device_compatible_entry compat_data[] = { 94 { .id = SUNW(PCI_PRODUCT_SUN_GEMNETWORK), 95 .value = GEM_SUN_GEM }, 96 97 { .id = SUNW(PCI_PRODUCT_SUN_ERINETWORK), 98 .value = GEM_SUN_ERI }, 99 100 { .id = AAPL(PCI_PRODUCT_APPLE_GMAC), 101 .value = GEM_APPLE_GMAC }, 102 103 { .id = AAPL(PCI_PRODUCT_APPLE_GMAC2), 104 .value = GEM_APPLE_GMAC }, 105 106 { .id = AAPL(PCI_PRODUCT_APPLE_GMAC3), 107 .value = GEM_APPLE_GMAC }, 108 109 { .id = AAPL(PCI_PRODUCT_APPLE_SHASTA_GMAC), 110 .value = GEM_APPLE_GMAC }, 111 112 { .id = AAPL(PCI_PRODUCT_APPLE_INTREPID2_GMAC), 113 .value = GEM_APPLE_GMAC }, 114 115 { .id = AAPL(PCI_PRODUCT_APPLE_K2_GMAC), 116 .value = GEM_APPLE_K2_GMAC }, 117 118 PCI_COMPAT_EOL 119 }; 120 121 #undef SUNW 122 #undef AAPL 123 124 /* 125 * Attach routines need to be split out to different bus-specific files. 126 */ 127 128 int 129 gem_pci_match(device_t parent, cfdata_t cf, void *aux) 130 { 131 struct pci_attach_args *pa = aux; 132 133 return pci_compatible_match(pa, compat_data); 134 } 135 136 static inline int 137 gempromvalid(u_int8_t* buf) 138 { 139 return buf[0] == 0x18 && buf[1] == 0x00 && /* structure length */ 140 buf[2] == 0x00 && /* revision */ 141 (buf[3] == 0x00 || /* hme */ 142 buf[3] == 0x80) && /* qfe */ 143 buf[4] == PCI_SUBCLASS_NETWORK_ETHERNET && /* subclass code */ 144 buf[5] == PCI_CLASS_NETWORK; /* class code */ 145 } 146 147 static inline int 148 isshared_pins(u_int8_t* buf) 149 { 150 return buf[0] == 's' && buf[1] == 'h' && buf[2] == 'a' && 151 buf[3] == 'r' && buf[4] == 'e' && buf[5] == 'd' && 152 buf[6] == '-' && buf[7] == 'p' && buf[8] == 'i' && 153 buf[9] == 'n' && buf[10] == 's'; 154 } 155 156 static inline int 157 isserdes(u_int8_t* buf) 158 { 159 return buf[0] == 's' && buf[1] == 'e' && buf[2] == 'r' && 160 buf[3] == 'd' && buf[4] == 'e' && buf[5] == 's'; 161 } 162 163 #define GEM_TMP_BUFSIZE 0x0800 164 165 void 166 gem_pci_attach(device_t parent, device_t self, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 struct gem_pci_softc *gsc = device_private(self); 170 struct gem_softc *sc = &gsc->gsc_gem; 171 const struct device_compatible_entry *dce; 172 uint8_t enaddr[ETHER_ADDR_LEN]; 173 bus_space_handle_t romh; 174 uint8_t *buf; 175 int dataoff, vpdoff, serdes; 176 int i, got_addr = 0; 177 #ifdef GEM_DEBUG 178 int j; 179 #endif 180 struct pci_vpd *vpd; 181 static const u_int8_t promhdr[] = { 0x55, 0xaa }; 182 #define PROMHDR_PTR_DATA 0x18 183 static const u_int8_t promdat[] = { 184 0x50, 0x43, 0x49, 0x52, /* "PCIR" */ 185 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 186 PCI_PRODUCT_SUN_GEMNETWORK & 0xff, 187 PCI_PRODUCT_SUN_GEMNETWORK >> 8 188 }; 189 #define PROMDATA_PTR_VPD 0x08 190 #define PROMDATA_DATA2 0x0a 191 192 pci_aprint_devinfo(pa, "Ethernet controller"); 193 194 sc->sc_dev = self; 195 sc->sc_chiprev = PCI_REVISION(pa->pa_class); 196 197 /* 198 * Some Sun GEMs/ERIs do have their intpin register bogusly set to 0, 199 * although it should be 1. correct that. 200 */ 201 if (pa->pa_intrpin == 0) 202 pa->pa_intrpin = 1; 203 204 dce = pci_compatible_lookup(pa, compat_data); 205 KASSERT(dce != NULL); 206 sc->sc_variant = (u_int)dce->value; 207 aprint_debug_dev(sc->sc_dev, "variant = %u\n", sc->sc_variant); 208 209 if (pci_dma64_available(pa)) 210 sc->sc_dmatag = pa->pa_dmat64; 211 else 212 sc->sc_dmatag = pa->pa_dmat; 213 214 sc->sc_flags |= GEM_PCI; 215 216 #define PCI_GEM_BASEADDR (PCI_MAPREG_START + 0x00) 217 218 /* XXX Need to check for a 64-bit mem BAR? */ 219 if (pci_mapreg_map(pa, PCI_GEM_BASEADDR, 220 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 221 &sc->sc_bustag, &sc->sc_h1, NULL, &sc->sc_size) != 0) 222 { 223 aprint_error_dev(sc->sc_dev, 224 "unable to map device registers\n"); 225 return; 226 } 227 if (bus_space_subregion(sc->sc_bustag, sc->sc_h1, 228 GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE, &sc->sc_h2)) { 229 aprint_error_dev(sc->sc_dev, 230 "unable to create bank 2 subregion\n"); 231 return; 232 } 233 234 buf = kmem_zalloc(GEM_TMP_BUFSIZE, KM_SLEEP); 235 236 if (ether_getaddr(sc->sc_dev, enaddr)) { 237 got_addr = 1; 238 if (device_getprop_data(sc->sc_dev, "shared-pins", 239 buf, GEM_TMP_BUFSIZE) > 0) { 240 if (isserdes(buf)) { 241 sc->sc_flags |= GEM_SERDES; 242 } 243 } 244 } else { 245 /* 246 * Dig out VPD (vital product data) and acquire Ethernet 247 * address. The VPD of gem resides in the PCI PROM (PCI FCode). 248 */ 249 /* 250 * ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and 251 * later) chapter 2 describes the data structure. 252 */ 253 254 uint8_t *enp = NULL; 255 256 if (sc->sc_variant == GEM_SUN_GEM && 257 (bus_space_subregion(sc->sc_bustag, sc->sc_h1, 258 GEM_PCI_ROM_OFFSET, GEM_PCI_ROM_SIZE, &romh)) == 0) { 259 260 /* read PCI Expansion PROM Header */ 261 bus_space_read_region_1(sc->sc_bustag, 262 romh, 0, buf, GEM_TMP_BUFSIZE); 263 264 /* Check for "shared-pins = serdes" in FCode. */ 265 i = 0; 266 serdes = 0; 267 while (i < GEM_TMP_BUFSIZE - sizeof "serdes") { 268 if (!serdes) { 269 if (isserdes(&buf[i])) 270 serdes = 1; 271 } else { 272 if (isshared_pins(&buf[i])) 273 serdes = 2; 274 } 275 if (serdes == 2) { 276 sc->sc_flags |= GEM_SERDES; 277 break; 278 } 279 i++; 280 } 281 #ifdef GEM_DEBUG 282 /* PROM dump */ 283 printf("%s: PROM dump (0x0000 to %04x)\n", 284 device_xname(sc->sc_dev), GEM_TMP_BUFSIZE - 1); 285 i = 0; 286 j = 0; 287 printf(" %04x ", i); 288 while (i < GEM_TMP_BUFSIZE ) { 289 printf("%02x ", buf[i]); 290 if (i && !(i % 8)) 291 printf(" "); 292 if (i && !(i % 16)) { 293 printf(" "); 294 while (j < i) { 295 if (buf[j] > 31 && buf[j] < 128) 296 printf("%c", buf[j]); 297 else 298 printf("."); 299 j++; 300 } 301 j = i; 302 printf("\n %04x ", i); 303 } 304 i++; 305 } 306 printf("\n"); 307 #endif 308 309 if (memcmp(buf, promhdr, sizeof promhdr) == 0 && 310 (dataoff = (buf[PROMHDR_PTR_DATA] | 311 (buf[PROMHDR_PTR_DATA + 1] << 8))) >= 0x1c) { 312 313 /* read PCI Expansion PROM Data */ 314 bus_space_read_region_1(sc->sc_bustag, romh, 315 dataoff, buf, 64); 316 if (memcmp(buf, promdat, sizeof promdat) == 0 && 317 gempromvalid(buf + PROMDATA_DATA2) && 318 (vpdoff = (buf[PROMDATA_PTR_VPD] | 319 (buf[PROMDATA_PTR_VPD + 1] << 8))) >= 0x1c) { 320 321 /* 322 * The VPD of gem is not in PCI 2.2 323 * standard format. The length in the 324 * resource header is in big endian, 325 * and resources are not properly 326 * terminated (only one resource and no 327 * end tag). 328 */ 329 /* read PCI VPD */ 330 bus_space_read_region_1(sc->sc_bustag, 331 romh, vpdoff, buf, 64); 332 vpd = (void *)(buf + 3); 333 if (PCI_VPDRES_ISLARGE(buf[0]) && 334 PCI_VPDRES_LARGE_NAME(buf[0]) 335 == PCI_VPDRES_TYPE_VPD && 336 vpd->vpd_key0 == 0x4e /* N */ && 337 vpd->vpd_key1 == 0x41 /* A */ && 338 vpd->vpd_len == ETHER_ADDR_LEN) { 339 /* 340 * Ethernet address found 341 */ 342 enp = buf + 6; 343 } 344 } 345 } 346 } 347 348 if (enp) { 349 memcpy(enaddr, enp, ETHER_ADDR_LEN); 350 got_addr = 1; 351 } 352 } 353 354 kmem_free(buf, GEM_TMP_BUFSIZE); 355 356 if (!got_addr) { 357 printf("%s: no Ethernet address found\n", 358 device_xname(sc->sc_dev)); 359 /* should we bail here? */ 360 } 361 362 if (pci_intr_map(pa, &gsc->gsc_handle) != 0) { 363 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 364 return; 365 } 366 gsc->gsc_pc = pa->pa_pc; 367 gem_pci_estintr(gsc); 368 369 /* Finish off the attach. */ 370 gem_attach(sc, enaddr); 371 372 if (pmf_device_register1(sc->sc_dev, 373 gem_pci_suspend, gem_pci_resume, gem_shutdown)) 374 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 375 else 376 aprint_error_dev(sc->sc_dev, 377 "could not establish power handlers\n"); 378 } 379 380 static bool 381 gem_pci_suspend(device_t self, const pmf_qual_t *qual) 382 { 383 struct gem_pci_softc *gsc = device_private(self); 384 385 if (gsc->gsc_ih != NULL) { 386 pci_intr_disestablish(gsc->gsc_pc, gsc->gsc_ih); 387 gsc->gsc_ih = NULL; 388 } 389 390 return true; 391 } 392 393 static bool 394 gem_pci_estintr(struct gem_pci_softc *gsc) 395 { 396 struct gem_softc *sc = &gsc->gsc_gem; 397 const char *intrstr; 398 char intrbuf[PCI_INTRSTR_LEN]; 399 400 intrstr = pci_intr_string(gsc->gsc_pc, gsc->gsc_handle, intrbuf, 401 sizeof(intrbuf)); 402 gsc->gsc_ih = pci_intr_establish_xname(gsc->gsc_pc, gsc->gsc_handle, 403 IPL_NET, gem_intr, sc, device_xname(sc->sc_dev)); 404 if (gsc->gsc_ih == NULL) { 405 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 406 if (intrstr != NULL) 407 aprint_error(" at %s", intrstr); 408 aprint_error("\n"); 409 return false; 410 } 411 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 412 return true; 413 } 414 415 static bool 416 gem_pci_resume(device_t self, const pmf_qual_t *qual) 417 { 418 struct gem_pci_softc *gsc = device_private(self); 419 420 return gem_pci_estintr(gsc); 421 } 422 423 static int 424 gem_pci_detach(device_t self, int flags) 425 { 426 int rc; 427 struct gem_pci_softc *gsc = device_private(self); 428 struct gem_softc *sc = &gsc->gsc_gem; 429 430 switch (sc->sc_att_stage) { 431 case GEM_ATT_BACKEND_2: 432 pmf_device_deregister(self); 433 sc->sc_att_stage = GEM_ATT_FINISHED; 434 /*FALLTHROUGH*/ 435 default: 436 if ((rc = gem_detach(sc, flags)) != 0) 437 return rc; 438 /*FALLTHROUGH*/ 439 case GEM_ATT_BACKEND_1: 440 if (gsc->gsc_ih != NULL) 441 pci_intr_disestablish(gsc->gsc_pc, gsc->gsc_ih); 442 443 bus_space_unmap(sc->sc_bustag, sc->sc_h1, sc->sc_size); 444 /*FALLTHROUGH*/ 445 case GEM_ATT_BACKEND_0: 446 sc->sc_att_stage = GEM_ATT_BACKEND_0; 447 break; 448 } 449 return 0; 450 } 451
Indexes created Sun Oct 12 22:09:51 GMT 2025