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    Searched refs:getAddressingMode (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGAddressAnalysis.cpp 189 if (N->getAddressingMode() == ISD::PRE_INC) {
194 } else if (N->getAddressingMode() == ISD::PRE_DEC) {
227 if (LSBase->getAddressingMode() == ISD::PRE_DEC ||
228 LSBase->getAddressingMode() == ISD::POST_DEC)
SelectionDAGDumper.cpp 701 const char *AM = getIndexedModeName(LD->getAddressingMode());
713 const char *AM = getIndexedModeName(ST->getAddressingMode());
733 const char *AM = getIndexedModeName(MLd->getAddressingMode());
748 const char *AM = getIndexedModeName(MSt->getAddressingMode());
LegalizeFloatTypes.cpp 687 NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
698 NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
2463 L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N),
2768 DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), MVT::i16,
LegalizeVectorTypes.cpp 1773 MMO, MLD->getAddressingMode(), ExtType,
1798 HiMemVT, MMO, MLD->getAddressingMode(), ExtType,
2615 N->getAddressingMode(), N->isTruncatingStore(),
2642 N->getAddressingMode(), N->isTruncatingStore(),
4068 PassThru, N->getMemoryVT(), N->getMemOperand(), N->getAddressingMode(),
4928 MST->getMemOperand(), MST->getAddressingMode(),
DAGCombiner.cpp 5628 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(),
5782 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
10732 PassThru, Ld->getMemoryVT(), Ld->getMemOperand(), Ld->getAddressingMode(),
11947 Ld->getAddressingMode(), ISD::SEXTLOAD, Ld->isExpandingLoad());
15439 ISD::MemIndexedMode AM = LD->getAddressingMode();
22736 Offset = (LSN->getAddressingMode() == ISD::PRE_INC)
22738 : (LSN->getAddressingMode() == ISD::PRE_DEC)
LegalizeIntegerTypes.cpp 705 N->getAddressingMode(), ISD::EXTLOAD);
1852 N->getMemOperand(), N->getAddressingMode(),
TargetLowering.cpp 7461 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
7613 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SelectionDAGNodes.h 2225 assert(getAddressingMode() == AM && "Value truncated");
2234 ISD::MemIndexedMode getAddressingMode() const {
2239 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2242 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2320 assert(getAddressingMode() == AM && "Value truncated");
2335 ISD::MemIndexedMode getAddressingMode() const {
2340 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2343 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2669 Ld->getAddressingMode() == ISD::UNINDEXED;
2699 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelDAGToDAG.cpp 123 ISD::MemIndexedMode AM = LD->getAddressingMode();
170 ISD::MemIndexedMode AM = LD->getAddressingMode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 817 ? cast<LoadSDNode>(Op)->getAddressingMode()
818 : cast<StoreSDNode>(Op)->getAddressingMode();
853 ? cast<LoadSDNode>(Op)->getAddressingMode()
854 : cast<StoreSDNode>(Op)->getAddressingMode();
873 ? cast<LoadSDNode>(Op)->getAddressingMode()
874 : cast<StoreSDNode>(Op)->getAddressingMode();
952 ? cast<LoadSDNode>(Op)->getAddressingMode()
953 : cast<StoreSDNode>(Op)->getAddressingMode();
1071 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1381 ? cast<LoadSDNode>(Op)->getAddressingMode()
    [all...]
ARMISelLowering.cpp 9635 N->getMemoryVT(), N->getMemOperand(), N->getAddressingMode(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 299 ISD::MemIndexedMode AM = LD->getAddressingMode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 450 ISD::MemIndexedMode AM = LD->getAddressingMode();
559 ISD::MemIndexedMode AM = ST->getAddressingMode();
HexagonISelLowering.cpp 2895 LN->getAddressingMode(), LN->getExtensionType(), MVT::i1, dl,
2929 SN->getAddressingMode());
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 5115 ST->getAddressingMode() != ISD::PRE_INC)
5126 if (LD->getAddressingMode() != ISD::PRE_INC) {
PPCISelLowering.cpp 8192 assert(LD->getAddressingMode() == ISD::PRE_INC &&
14894 assert(LD->getAddressingMode() == ISD::PRE_INC &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 1274 ISD::MemIndexedMode AM = LD->getAddressingMode();
AArch64ISelLowering.cpp 17375 Load->getMemoryVT(), Load->getMemOperand(), Load->getAddressingMode(),
17430 Load->getAddressingMode(), Load->getExtensionType());
17456 Store->getMemOperand(), Store->getAddressingMode(),
17477 Store->getAddressingMode(), Store->isTruncatingStore());
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 778 LD->getAddressingMode() != ISD::UNINDEXED ||
X86ISelLowering.cpp     [all...]

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