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  /src/external/apache2/llvm/dist/llvm/include/llvm/Option/
OptSpecifier.h 29 unsigned getID() const { return ID; }
31 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
OptTable.h 81 unsigned id = Opt.getID();
Option.h 87 unsigned getID() const {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp 63 return ContainedRegClasses.test(RC.getID());
76 assert((OtherRB.getID() != getID() || &OtherRB == this) &&
92 OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
  /src/external/apache2/llvm/dist/clang/lib/Frontend/
TextDiagnosticPrinter.cpp 58 if (Info.getID() == diag::fatal_too_many_errors) {
73 DiagnosticIDs::isBuiltinWarningOrExtension(Info.getID()) &&
74 !DiagnosticIDs::isDefaultMappingAsError(Info.getID())) {
79 StringRef Opt = DiagnosticIDs::getWarningOptionForDiag(Info.getID());
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID());
  /src/external/apache2/llvm/dist/clang/tools/libclang/
CXStoredDiagnostic.cpp 53 unsigned ID = Diag.getID();
71 return DiagnosticIDs::getCategoryNumberForDiag(Diag.getID());
75 unsigned catID = DiagnosticIDs::getCategoryNumberForDiag(Diag.getID());
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 64 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF);
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
334 && TLI->getRegClassFor(VT)->getID() == RCId)
345 && TLI->getRegClassFor(VT)->getID() == RCId)
365 RegBalance += rawRegPressureDelta(SU, RC->getID());
369 if ((RegPressure[RC->getID()] +
370 rawRegPressureDelta(SU, RC->getID()) > 0) &&
371 (RegPressure[RC->getID()] +
372 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBank.h 47 unsigned getID() const { return ID; }
RegisterBankInfo.h 231 unsigned getID() const { return ID; }
255 return getID() != InvalidMappingID && OperandsMapping;
709 /// \p OpdMapper.getInstrMapping().getID() carries the information of
717 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.cpp 92 switch (RC->getID()) {
357 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
359 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
360 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
428 switch (RC.getID()) {
HexagonMachineScheduler.cpp 588 << ((Q.getID() == TopQID) ? "(top|" : "(bot|"));
597 if (Q.getID() == TopQID) {
640 if (Q.getID() == TopQID) {
676 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 &&
692 if (Q.getID() == TopQID &&
696 } else if (Q.getID() == BotQID &&
705 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) {
714 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) {
731 if (Q.getID() == TopQID) {
798 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum
    [all...]
  /src/external/apache2/llvm/dist/clang/include/clang/AST/
CommentCommandTraits.h 33 unsigned getID() const {
  /src/external/apache2/llvm/dist/llvm/lib/Option/
Option.cpp 100 if (getID() == Opt.getID())
242 if (getID() == UnaliasedOption.getID())
ArgList.cpp 40 OptRanges.insert(std::make_pair(O.getID(), emptyRange())).first->second;
54 OptRanges.erase(Id.getID());
61 auto I = OptRanges.find(Id.getID());
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 193 assert((RegBank->getID() == ARM::GPRRegBankID ||
194 RegBank->getID() == ARM::FPRRegBankID) &&
197 if (RegBank->getID() == ARM::FPRRegBankID) {
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineScheduler.cpp 519 unsigned PredID = Pred->getID();
523 if (PredID == P->getID())
531 return PredID == S.first->getID();
538 unsigned SuccID = Succ->getID();
542 if (SuccID == S.first->getID()) {
554 [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) &&
630 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID;
1287 if (!--TopDownBlock2Index[Pred->getID()])
1288 WorkList.push_back(Pred->getID());
1297 assert(TopDownBlock2Index[i] > TopDownBlock2Index[Pred->getID()] &
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
DAGISelEmitter.cpp 118 return LHS->getID() < RHS->getID();
  /src/external/apache2/llvm/dist/clang/tools/diagtool/
DiagnosticNames.h 68 inline short getID() const {
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 77 const RCInfo &RCI = RegClass[RC->getID()];
StackMaps.h 47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); }
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); }
TargetRegisterInfo.h 69 unsigned getID() const { return MC->getID(); }
125 unsigned ID = RC->getID();
720 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
1230 bool isValid() const { return getID() != NumRegClasses; }
1233 unsigned getID() const { return ID; }
  /src/external/apache2/llvm/dist/llvm/tools/llvm-readobj/
StackMapPrinter.h 39 W.startLine() << " Record ID: " << R.getID()
  /src/external/apache2/llvm/dist/clang/lib/ARCMigrate/
TransProtectedScope.cpp 120 if (I->getID() == diag::err_switch_into_protected_scope &&
133 assert(DiagI->getID() == diag::err_switch_into_protected_scope);
159 Pass.TA.clearDiagnostic(Diag.getID(), Diag.getLocation());
PlistReporter.cpp 96 DiagIDs.getCategoryNumberForDiag(D.getID()))) << '\n';
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
MemorySSA.h 129 // getID()
219 inline unsigned getID() const;
341 OptimizedID = DMA->getID();
346 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
400 OptimizedID = MA->getID();
408 return getOptimized() && OptimizedID == getOptimized()->getID();
418 unsigned getID() const { return ID; }
636 unsigned getID() const { return ID; }
665 inline unsigned MemoryAccess::getID() const {
669 return MD->getID();
    [all...]

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