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    Searched refs:getImplicitDefs (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 581 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
MCInstrDescView.cpp 131 for (const MCPhysReg *MCPhysReg = Description->getImplicitDefs();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGFast.cpp 435 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
514 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
ScheduleDAGRRList.cpp 1286 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1427 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
2845 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2881 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2888 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
InstrEmitter.cpp 928 II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
1031 Register Reg = II.getImplicitDefs()[i - NumDefs];
1066 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
ScheduleDAGSDNodes.cpp 466 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
InstrBuilder.cpp 353 Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb2SizeReduction.cpp 255 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCChecker.cpp 102 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RDFGraph.cpp 628 if (!D.getImplicitDefs() && !D.getImplicitUses())
637 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
MachineInstr.cpp 106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 459 const MCPhysReg Reg = Desc.getImplicitDefs()[I];
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 1204 for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCParser/
AsmParser.cpp 6005 ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(),
MasmParser.cpp 7138 ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 2709 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 3220 if (const MCPhysReg *ImpDef = MI.getDesc().getImplicitDefs()) {

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