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    Searched refs:getInstr (Results 1 - 25 of 87) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
DebugHandlerBase.cpp 299 Entries.front().getInstr()->getDebugVariable();
302 Entries.front().getInstr()->getParent()->sameSection(&MF->front())) {
303 if (!IsDescribedByReg(Entries.front().getInstr()))
304 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin();
305 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) {
310 const DIExpression *Fragment = I->getInstr()->getDebugExpression();
315 Pred.getInstr()->getDebugExpression());
322 if (IsDescribedByReg(I->getInstr()))
324 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin();
331 requestLabelBeforeInsn(Entry.getInstr());
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DbgEntityHistoryCalculator.cpp 80 Entries.back().getInstr()->isIdenticalTo(MI)) {
82 << "\t" << Entries.back().getInstr() << "\t" << MI
96 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI)
198 const MachineInstr *StartMI = EI->getInstr();
200 ? HistoryMapEntries[EndIndex].getInstr()
265 const MachineInstr *MI = Entry.getInstr();
339 if (Entry.getInstr()->isDebugEntryValue())
341 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) {
344 for (auto &MO : Entry.getInstr()->debug_operands())
348 for (auto &MO : Entry.getInstr()->debug_operands()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHazardRecognizer.cpp 40 MachineInstr *MI = SU->getInstr();
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())
109 MachineInstr *MI = SU->getInstr();
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) {
HexagonSubtarget.cpp 216 MachineInstr &MI1 = *SU.getInstr();
225 MachineInstr &MI2 = *SI.getSUnit()->getInstr();
253 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
257 unsigned Type = HII.getType(*Inst2.getInstr());
277 if (DAG->SUnits[su].getInstr()->isCall())
280 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
301 const MachineInstr *MI = DAG->SUnits[su].getInstr();
343 MachineInstr &L0 = *S0.getInstr();
356 MachineInstr &L1 = *S1.getInstr();
395 MachineInstr *SrcInst = Src->getInstr();
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HexagonMachineScheduler.cpp 74 if (QII.mayBeCurLoad(*SUd->getInstr()))
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
98 if (!SU || !SU->getInstr())
103 switch (SU->getInstr()->getOpcode()) {
105 if (!ResourcesModel->canReserveResources(*SU->getInstr()))
119 MachineBasicBlock *MBB = SU->getInstr()->getParent();
157 switch (SU->getInstr()->getOpcode()) {
159 ResourcesModel->reserveResources(*SU->getInstr());
181 LLVM_DEBUG(Packet[i]->getInstr()->dump())
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HexagonVLIWPacketizer.cpp 424 if (PacketSU->getInstr()->isInlineAsm())
518 assert(SUI->getInstr() && SUJ->getInstr());
519 MachineInstr &MI = *SUI->getInstr();
520 MachineInstr &MJ = *SUJ->getInstr();
675 if (PacketSU->getInstr()->mayStore())
761 MachineInstr &TempMI = *TempSU->getInstr();
774 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
828 MachineInstr &PacketMI = *PacketSU->getInstr();
861 const MachineInstr &PI = *PacketSU->getInstr();
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SnippetGenerator.cpp 48 if (Variant.getInstr().hasMemoryOperands()) {
59 for (const auto &Op : Variant.getInstr().Operands) {
121 for (const Operand &Op : IT.getInstr().Operands) {
131 for (const Operand &Op : IT.getInstr().Operands) {
144 const AliasingConfigurations SelfAliasing(Variant.getInstr(),
145 Variant.getInstr());
264 for (const Variable &Var : IT.getInstr().Variables) {
267 if (auto Err = randomizeMCOperand(State, IT.getInstr(), Var,
SerialSnippetGenerator.cpp 51 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
118 const AliasingConfigurations SelfAliasing(Variant.getInstr(),
119 Variant.getInstr());
133 const Instruction &Instr = Variant.getInstr();
166 getExecutionModes(Variant.getInstr(), ForbiddenRegisters);
CodeTemplate.h 39 const Instruction &getInstr() const { return *Instr; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZHazardRecognizer.cpp 105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))
169 OS << TII->getName(SU->getInstr()->getOpcode());
204 if (has4RegOps(SU->getInstr()))
285 LastEmittedMI = SU->getInstr();
291 LastEmittedMI = SU->getInstr();
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr());
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))
SystemZHazardRecognizer.h 123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600MachineScheduler.cpp 156 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
157 E = SU->getInstr()->operands_end(); It != E; ++It) {
190 if (isPhysicalRegCopy(SU->getInstr())) {
215 MachineInstr *MI = SU->getInstr();
289 int Opcode = SU->getInstr()->getOpcode();
318 InstructionsGroupCandidate.push_back(SU->getInstr());
320 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) {
389 AssignSlot(UnslotedSU->getInstr(), Slot);
438 InstructionsGroupCandidate.push_back(SU->getInstr());
AMDGPUExportClustering.cpp 30 return SIInstrInfo::isEXP(*SU.getInstr());
34 const MachineInstr *MI = SU->getInstr();
GCNDPPCombine.cpp 240 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
262 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
272 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
273 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
288 DPPInst.getInstr()->eraseFromParent();
291 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr());
292 return DPPInst.getInstr();
486 DPPMIs.push_back(UndefInst.getInstr());
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MacroFusion.cpp 94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
161 if (DAG->ExitSU.getInstr())
169 const MachineInstr &AnchorMI = *AnchorSU.getInstr();
188 const MachineInstr *DepMI = DepSU.getInstr();
SlotIndexes.cpp 125 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken.");
138 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken.");
217 MachineInstr *SlotMI = ListI->getInstr();
254 if (ILE.getInstr()) {
255 dbgs() << *ILE.getInstr();
ScheduleDAGInstrs.cpp 234 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
242 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
264 RegUse = UseSU->getInstr();
267 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr);
272 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
279 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle()))
292 MachineInstr *MI = SU->getInstr();
317 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
321 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
396 MachineInstr *MI = SU->getInstr();
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MachinePipeliner.cpp 617 OrderedInsts.push_back(SU->getInstr());
618 Cycles[SU->getInstr()] = Cycle;
619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU);
745 MachineInstr &MI = *SU.getInstr();
770 MachineInstr &LdMI = *Load->getInstr();
846 MachineInstr *MI = I.getInstr();
902 MachineInstr *PMI = PI.getSUnit()->getInstr();
904 if (I.getInstr()->isPHI()) {
927 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase,
932 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg()
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  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/
Target.cpp 19 const auto Op = IT.getInstr().Operands[OpIdx];
77 if (IT.getInstr().hasTiedRegisters())
80 const auto DispOp = IT.getInstr().Operands[DispOpIdx];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 45 MachineInstr *MI = SU->getInstr();
88 MachineInstr *MI = SU->getInstr();
183 MachineInstr &L0 = *SU->getInstr();
255 MachineInstr &MI = *SU->getInstr();
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMachineScheduler.cpp 25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/
Target.cpp 44 const auto Op = IT.getInstr().Operands[OpIdx];
140 assert(!isInvalidMemoryInstr(IT.getInstr()) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kInstrInfo.cpp 373 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n');
376 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n");
388 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to ");
419 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc);
424 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst);
427 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst);
438 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and ");
456 MachineBasicBlock::iterator I = MIB.getInstr();
474 MachineBasicBlock::iterator I = MIB.getInstr();
510 auto MI = MIB.getInstr();
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
DbgEntityHistoryCalculator.h 82 const MachineInstr *getInstr() const { return Instr.getPointer(); }
SlotIndexes.h 53 MachineInstr* getInstr() const { return mi; }
404 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
413 if (I->getInstr())
598 assert(miEntry->getInstr() == &MI &&

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