| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRExpandPseudoInsts.cpp | 156 .addReg(DstLoReg, getKillRegState(DstIsKill))
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
161 .addReg(DstHiReg, getKillRegState(DstIsKill))
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
189 .addReg(DstLoReg, getKillRegState(DstIsKill))
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
197 .addReg(DstHiReg, getKillRegState(DstIsKill))
198 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
237 .addReg(DstLoReg, getKillRegState(SrcIsKill))
247 .addReg(DstHiReg, getKillRegState(SrcIsKill)
[all...] |
| AVRRelaxMemOperations.cpp | 112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill()));
|
| AVRInstrInfo.cpp | 53 .addReg(SrcReg, getKillRegState(KillSrc));
62 .addReg(SrcLo, getKillRegState(KillSrc));
64 .addReg(SrcHi, getKillRegState(KillSrc));
78 .addReg(SrcReg, getKillRegState(KillSrc));
155 .addReg(SrcReg, getKillRegState(isKill))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 323 .addReg(SrcReg, getKillRegState(KillSrc));
331 .addReg(SrcReg, getKillRegState(KillSrc));
335 .addReg(SrcReg, getKillRegState(KillSrc));
346 .addReg(SrcReg, getKillRegState(KillSrc));
363 .addReg(SrcReg, getKillRegState(KillSrc));
367 .addReg(SrcReg, getKillRegState(KillSrc));
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 53 .addReg(SrcReg, getKillRegState(KillSrc))
63 .addReg(SrcReg, getKillRegState(KillSrc))
71 .addReg(SrcReg, getKillRegState(KillSrc));
98 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 291 .addReg(Src1Reg, getKillRegState(Src1Kill))
292 .addReg(Src2Reg, getKillRegState(Src2Kill));
302 MIB.addReg(TmpReg, getKillRegState(true))
303 .addReg(AccReg, getKillRegState(AccKill));
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMLoadStoreOptimizer.cpp | 744 .addReg(Base, getKillRegState(KillOldBase));
747 .addReg(Base, getKillRegState(KillOldBase))
757 .addReg(Base, getKillRegState(KillOldBase))
763 .addReg(Base, getKillRegState(KillOldBase))
768 .addReg(Base, getKillRegState(KillOldBase))
810 .addReg(Base, getKillRegState(BaseKill));
819 MIB.addReg(Base, getKillRegState(BaseKill));
825 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
849 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
850 .addReg(Regs[1].first, getKillRegState(Regs[1].second))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 37 .addReg(SrcReg, getKillRegState(KillSrc));
40 .addReg(SrcReg, getKillRegState(KillSrc));
135 .addReg(SrcReg, getKillRegState(IsKill))
140 .addReg(SrcReg, getKillRegState(IsKill))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kInstrBuilder.h | 51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| X86LowerTileCopy.cpp | 115 .addReg(SrcReg, getKillRegState(SrcMO.isKill()));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 278 .addReg(Src, getKillRegState(IsKill));
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
103 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
|
| XCoreInstrInfo.cpp | 340 .addReg(SrcReg, getKillRegState(KillSrc))
352 .addReg(SrcReg, getKillRegState(KillSrc));
375 .addReg(SrcReg, getKillRegState(isKill))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEInstrInfo.cpp | 366 .addReg(SrcReg, getKillRegState(KillSrc))
384 .addReg(SrcReg, getKillRegState(KillSrc))
385 .addReg(SubTmp, getKillRegState(true));
390 .addReg(SrcReg, getKillRegState(KillSrc));
476 .addReg(SrcReg, getKillRegState(isKill))
483 .addReg(SrcReg, getKillRegState(isKill))
490 .addReg(SrcReg, getKillRegState(isKill))
497 .addReg(SrcReg, getKillRegState(isKill))
899 .addReg(Src, getKillRegState(KillSrc));
913 .addReg(Src, getKillRegState(KillSrc)
[all...] |
| VEISelLowering.cpp | 1822 .addReg(Tmp1, getKillRegState(true))
1826 .addReg(Tmp2, getKillRegState(true))
1838 .addReg(Tmp1, getKillRegState(true))
1841 .addReg(Tmp2, getKillRegState(true))
1883 .addReg(Tmp1, getKillRegState(true))
1887 .addReg(Tmp2, getKillRegState(true))
1903 .addReg(Tmp1, getKillRegState(true))
1907 .addReg(Tmp2, getKillRegState(true))
1910 .addReg(Tmp3, getKillRegState(true))
1926 .addReg(Tmp1, getKillRegState(true)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVRegisterInfo.cpp | 264 .addReg(FrameReg, getKillRegState(FrameRegIsKill))
279 .addReg(FrameReg, getKillRegState(FrameRegIsKill))
286 .addReg(FrameReg, getKillRegState(FrameRegIsKill))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
139 .addReg(SrcReg, getKillRegState(KillSrc));
180 MIB.addReg(SrcReg, getKillRegState(KillSrc));
314 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
753 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
754 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
764 unsigned KillSrc = getKillRegState(Src.isKill());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 725 .addReg(VReg1, getKillRegState(true))
927 .addReg(RegX, getKillRegState(KillX))
928 .addReg(RegM21, getKillRegState(KillM21))
929 .addReg(RegM22, getKillRegState(KillM22));
932 .addReg(RegY, getKillRegState(KillY))
933 .addReg(RegM31, getKillRegState(KillM31))
934 .addReg(RegM32, getKillRegState(KillM32));
944 .addReg(NewVRB, getKillRegState(true))
945 .addReg(NewVRA, getKillRegState(true));
964 .addReg(RegM11, getKillRegState(KillM11)
[all...] |
| PPCRegisterInfo.cpp | 591 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
599 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
679 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
696 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
796 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
956 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
1089 .addReg(Reg, getKillRegState(IsKilled)),
1092 .addReg(Reg + 1, getKillRegState(IsKilled)),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 694 .addReg(cmpReg1, getKillRegState(MO1IsKill))
695 .addReg(cmpOp2, getKillRegState(MO2IsKill))
700 .addReg(cmpReg1, getKillRegState(MO1IsKill))
|
| HexagonStoreWidening.cpp | 435 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
458 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCInstrInfo.cpp | 290 .addReg(SrcReg, getKillRegState(KillSrc));
316 .addReg(SrcReg, getKillRegState(isKill))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 79 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
263 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
785 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
806 .addReg(SrcRegHi, getKillRegState(KillSrc))
807 .addReg(SrcRegLo, getKillRegState(KillSrc));
822 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
831 .addReg(SrcReg, getKillRegState(KillSrc))
859 .addReg(SrcReg, getKillRegState(KillSrc));
873 .addReg(SrcReg, getKillRegState(isKill))
[all...] |
