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    Searched refs:getMachineOpcode (Results 1 - 25 of 27) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.cpp 83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
127 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
212 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
317 unsigned Opc = Node->getMachineOpcode();
376 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
394 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
451 unsigned Opc = MainNode->getMachineOpcode();
466 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
471 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
557 unsigned POpc = Node->getMachineOpcode();
    [all...]
ResourcePriorityQueue.cpp 255 switch (SU->getNode()->getMachineOpcode()) {
258 SU->getNode()->getMachineOpcode())))
295 switch (SU->getNode()->getMachineOpcode()) {
298 SU->getNode()->getMachineOpcode()));
440 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
542 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
544 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
ScheduleDAGRRList.cpp 331 unsigned Opcode = Node->getMachineOpcode();
458 if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
460 } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
514 if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
517 } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
581 Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
787 SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
858 SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
875 SUNode->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
1034 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
    [all...]
InstrEmitter.cpp 135 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
197 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
204 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
277 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
478 unsigned Opc = Node->getMachineOpcode();
876 unsigned Opc = Node->getMachineOpcode();
1051 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1110 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
ScheduleDAGFast.cpp 254 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
432 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
511 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
SelectionDAGDumper.cpp 67 if (getMachineOpcode() < TII->getNumOpcodes())
68 return std::string(TII->getName(getMachineOpcode()));
SelectionDAGISel.cpp 3736 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 859 Use->isMachineOpcode() ? Use->getMachineOpcode() : Use->getOpcode();
2836 bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8;
2847 LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG)
2859 uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode();
6153 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
6154 User->getMachineOpcode() != PPC::SELECT_I8)
6167 if (Op2->getMachineOpcode() != PPC::LI &&
6168 Op2->getMachineOpcode() != PPC::LI8)
6187 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
6188 User->getMachineOpcode() == PPC::SELECT_I8) &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
Thumb1InstrInfo.cpp 150 unsigned Opcode = N->getMachineOpcode();
ARMBaseInstrInfo.cpp 1933 switch (Load1->getMachineOpcode()) {
1954 switch (Load2->getMachineOpcode()) {
2021 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
2022 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
2023 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
2024 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
2025 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
4433 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4448 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetInstrInfo.cpp 1098 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1101 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1113 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
ScheduleDAG.cpp 72 return &TII->get(Node->getMachineOpcode());
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SelectionDAGNodes.h 210 inline unsigned getMachineOpcode() const;
620 /// post-isel opcodes, see getMachineOpcode.
678 unsigned getMachineOpcode() const {
1145 inline unsigned SDValue::getMachineOpcode() const {
1146 return Node->getMachineOpcode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 1362 unsigned Opc = N->getMachineOpcode();
1371 N0.getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG ||
1379 if (!N00.isMachineOpcode() || N00.getMachineOpcode() != ExpectedOpc)
1417 unsigned Opc = N->getMachineOpcode();
1424 unsigned N0Opc = And.getMachineOpcode();
1474 unsigned N0Opc = And.getMachineOpcode();
1511 switch (Move.getMachineOpcode()) {
1533 In.getMachineOpcode() <= TargetOpcode::GENERIC_OP_END)
1538 uint64_t TSFlags = getInstrInfo()->get(In.getMachineOpcode()).TSFlags;
2827 unsigned Opc = N->getMachineOpcode();
    [all...]
X86InstrInfo.cpp 6404 const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6552 unsigned Opc1 = Load1->getMachineOpcode();
6553 unsigned Opc2 = Load2->getMachineOpcode();
6753 unsigned Opc1 = Load1->getMachineOpcode();
6754 unsigned Opc2 = Load2->getMachineOpcode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 1452 switch (N->getMachineOpcode()) {
1486 if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1988 switch (Src.getMachineOpcode()) {
2002 unsigned Opcode = ParentNode->getMachineOpcode();
2067 if (Src.getMachineOpcode() == R600::MOV_IMM_F32) {
2117 unsigned Opcode = Node->getMachineOpcode();
AMDGPUISelDAGToDAG.cpp 570 switch (N->getMachineOpcode()) {
573 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
2957 unsigned Opc = User->getMachineOpcode();
SIISelLowering.cpp 10958 unsigned Opcode = Node->getMachineOpcode();
10998 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
11055 AMDGPU::getMaskedMIMGOp(Node->getMachineOpcode(), NewChannels);
11057 NewOpcode != static_cast<int>(Node->getMachineOpcode()) &&
11177 unsigned Opcode = Node->getMachineOpcode();
11202 Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
11219 Src0.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
11221 Src1.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
11224 Src2.getMachineOpcode() != AMDGPU::IMPLICIT_DEF)
11227 assert(Src1.getMachineOpcode() == AMDGPU::IMPLICIT_DEF)
    [all...]
SIInstrInfo.cpp 84 unsigned Opc0 = N0->getMachineOpcode();
85 unsigned Opc1 = N1->getMachineOpcode();
135 unsigned Opc0 = Load0->getMachineOpcode();
136 unsigned Opc1 = Load1->getMachineOpcode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.h 369 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
HexagonISelDAGToDAG.cpp 221 uint64_t F = HII->get(LoadN->getMachineOpcode()).TSFlags;
1195 unsigned UseOpc = U->getMachineOpcode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 1778 CCRegUser->getMachineOpcode() == SystemZ::BRC)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 2076 unsigned NOpc = N->getMachineOpcode();
2293 switch (UserNode->getMachineOpcode()) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 4458 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {

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