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    Searched refs:getMaxNumSGPRs (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNSubtarget.h 1027 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
1028 return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable);
1042 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
AMDGPUSubtarget.cpp 730 unsigned GCNSubtarget::getMaxNumSGPRs(const MachineFunction &MF) const {
737 unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false);
738 unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, true);
763 if (Requested && Requested > getMaxNumSGPRs(WavesPerEU.first, false))
GCNSchedStrategy.cpp 44 SGPRCriticalLimit = ST.getMaxNumSGPRs(TargetOccupancy, true);
389 unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF);
SIRegisterInfo.cpp 438 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
497 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
2293 return std::min(ST.getMaxNumSGPRs(Occupancy, true), ST.getMaxNumSGPRs(MF));
2481 ST.getMaxNumSGPRs(MF) / 4);
2487 ST.getMaxNumSGPRs(MF) / 2);
2492 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.h 217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
AMDGPUBaseInfo.cpp 640 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,

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