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    Searched refs:getOpRegClass (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 664 if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) ||
813 TII->getOpRegClass(*UseMI, UseMI->getOperandNo(&Use));
SIInstrInfo.h 863 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
889 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
SIInstrInfo.cpp 292 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
296 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
1803 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2);
3952 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
4232 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
4484 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
5412 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {
5415 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) {
5418 VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
5422 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)
    [all...]
SIInsertWaitcnts.cpp 487 const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo);
SIISelLowering.cpp 11300 uint32_t DstSize = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
11305 Register PrevDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
11316 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));

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