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    Searched refs:getOpcodeDef (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 63 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI);
75 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI);
78 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI);
AArch64PostLegalizerLowering.cpp 321 auto *InsMI = getOpcodeDef(TargetOpcode::G_INSERT_VECTOR_ELT,
326 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(),
346 auto *BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR,
AArch64InstructionSelector.cpp 1498 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI);
1533 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI);
2142 MachineInstr *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
2145 Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
2966 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI);
4807 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI);
4811 else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT,
5352 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
5413 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI);
5486 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
Utils.h 201 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
LegalizationArtifactCombiner.h 324 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CombinerHelper.cpp 671 if (auto *LoadMI = getOpcodeDef(TargetOpcode::G_SEXTLOAD, LoadUser, MRI)) {
699 MachineInstr *LoadDef = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI);
831 MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI);
1234 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
1349 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
1455 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
2571 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
2578 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
2590 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
2596 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg()
    [all...]
Utils.cpp 418 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg,
LegalizerHelper.cpp 4466 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2585 if (MachineInstr *SrcFNeg = getOpcodeDef(AMDGPU::G_FNEG, ModSrc, MRI)) {
2587 if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI))
2589 } else if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI))
AMDGPUInstructionSelector.cpp 2192 MachineInstr *Fabs = getOpcodeDef(TargetOpcode::G_FABS, Src, *MRI);
4035 = getOpcodeDef(TargetOpcode::G_PTR_ADD, Data.N0, *MRI)) {
AMDGPURegisterBankInfo.cpp 1380 MachineInstr *Add = getOpcodeDef(AMDGPU::G_ADD, CombinedOffset, *MRI);

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