| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86InstComments.cpp | 251 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
316 Mul2Name = getRegName(MI->getOperand(2).getReg());
317 Mul1Name = getRegName(MI->getOperand(1).getReg());
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
322 Mul1Name = getRegName(MI->getOperand(1).getReg());
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
331 Mul2Name = getRegName(MI->getOperand(2).getReg());
332 Mul1Name = getRegName(MI->getOperand(1).getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUGlobalISelUtils.cpp | 24 const MachineOperand &Op = Def->getOperand(1);
36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
37 return std::make_pair(Def->getOperand(1).getReg(), Offset);
40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
41 return std::make_pair(Def->getOperand(1).getReg(), Offset);
47 if (mi_match(Def->getOperand(1).getReg(), MRI,
51 return std::make_pair(Base->getOperand(1).getReg(), Offset);
54 return std::make_pair(Base->getOperand(0).getReg(), Offset);
|
| R600ClauseMergePass.cpp | 78 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT))
85 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled))
102 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
127 if (LatrCFAlu.getOperand(Mode0Idx).getImm() &&
128 RootCFAlu.getOperand(Mode0Idx).getImm() &&
129 (LatrCFAlu.getOperand(KBank0Idx).getImm() !=
130 RootCFAlu.getOperand(KBank0Idx).getImm() ||
131 LatrCFAlu.getOperand(KBank0LineIdx).getImm() !=
132 RootCFAlu.getOperand(KBank0LineIdx).getImm())) {
143 if (LatrCFAlu.getOperand(Mode1Idx).getImm() &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVMergeBaseOffset.cpp | 83 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
84 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
85 HiLUI.getOperand(1).getOffset() != 0 ||
86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
91 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
92 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
93 LoADDI->getOperand(2).getOffset() != 0 ||
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
106 HiLUI.getOperand(1).setOffset(Offset)
[all...] |
| RISCVCleanupVSETVLI.cpp | 58 if (!PrevVSETVLI || !MI.getOperand(0).isDead())
62 int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm();
63 int64_t VTYPEImm = MI.getOperand(2).getImm();
73 return PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
77 Register AVLReg = MI.getOperand(1).getReg();
78 Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg();
81 if (AVLReg == RISCV::X0 && MI.getOperand(0).getReg() == RISCV::X0)
96 if (AVLReg != PrevVSETVLI->getOperand(1).getReg())
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/ |
| VEInstPrinter.cpp | 57 const MCOperand &MO = MI->getOperand(OpNum);
89 if (MI->getOperand(OpNum + 2).isImm() &&
90 MI->getOperand(OpNum + 2).getImm() == 0) {
95 if (MI->getOperand(OpNum + 1).isImm() &&
96 MI->getOperand(OpNum + 1).getImm() == 0 &&
97 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
98 if (MI->getOperand(OpNum + 2).isImm() &&
99 MI->getOperand(OpNum + 2).getImm() == 0) {
106 if (MI->getOperand(OpNum + 1).isImm() &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
130 Register AddendSrcReg = AddendMI->getOperand(1).getReg();
132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
186 Register OldFMAReg = MI.getOperand(0).getReg();
190 Register Reg2 = MI.getOperand(2).getReg();
191 Register Reg3 = MI.getOperand(3).getReg();
218 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg();
219 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg()
[all...] |
| PPCMIPeephole.cpp | 174 return MI->getOperand(3).getImm();
177 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
178 return MI->getOperand(3).getImm();
183 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
184 return 32 + MI->getOperand(3).getImm();
187 uint16_t Imm = MI->getOperand(2).getImm();
287 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg();
295 Register Reg = Instr->getOperand(1).getReg()
[all...] |
| PPCPreEmitPeephole.cpp | 133 if (!BBI->getOperand(1).isImm())
135 assert(BBI->getOperand(0).isReg() &&
140 Register Reg = BBI->getOperand(0).getReg();
141 int64_t Imm = BBI->getOperand(1).getImm();
143 if (BBI->getOperand(0).isDead()) {
144 DeadOrKillToUnset = &BBI->getOperand(0);
159 if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) {
168 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx);
180 assert(AfterBBI->getOperand(0).isReg() &&
184 if (!AfterBBI->getOperand(1).isImm() |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
37 .addImm(MI->getOperand(1).getImm());
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
42 .addImm(MI->getOperand(2).getImm());
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
51 .addImm(MI->getOperand(1).getImm());
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
56 .addImm(MI->getOperand(2).getImm())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
128 OutOps.push_back(Op.getOperand(0));
163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
164 N->getOperand(2) };
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
171 N->getOperand(2) };
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRExpandPseudoInsts.cpp | 145 Register DstReg = MI.getOperand(0).getReg();
146 Register SrcReg = MI.getOperand(2).getReg();
147 bool DstIsDead = MI.getOperand(0).isDead();
148 bool DstIsKill = MI.getOperand(1).isKill();
149 bool SrcIsKill = MI.getOperand(2).isKill();
150 bool ImpIsDead = MI.getOperand(3).isDead();
165 MIBHI->getOperand(3).setIsDead();
168 MIBHI->getOperand(4).setIsKill();
178 Register DstReg = MI.getOperand(0).getReg();
179 Register SrcReg = MI.getOperand(2).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/ |
| Annotation2Metadata.cpp | 40 C = cast<Constant>(C->getOperand(0));
50 auto *StrGEP = dyn_cast<ConstantExpr>(OpC->getOperand(1));
53 auto *StrC = dyn_cast<GlobalValue>(StrGEP->getOperand(0));
56 auto *StrData = dyn_cast<ConstantDataSequential>(StrC->getOperand(0));
60 auto *Bitcast = dyn_cast<ConstantExpr>(OpC->getOperand(0));
63 auto *Fn = dyn_cast<Function>(Bitcast->getOperand(0));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 97 DstReg = MI.getOperand(0).getReg();
98 Src1Reg = MI.getOperand(1).getReg();
99 Src2Reg = MI.getOperand(2).getReg();
111 DstReg = MI.getOperand(0).getReg();
112 SrcReg = MI.getOperand(1).getReg();
123 DstReg = MI.getOperand(0).getReg();
124 SrcReg = MI.getOperand(1).getReg();
133 DstReg = MI.getOperand(0).getReg();
142 DstReg = MI.getOperand(0).getReg();
143 Src1Reg = MI.getOperand(1).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiInstPrinter.cpp | 49 unsigned AluCode = MI->getOperand(3).getImm();
51 (MI->getOperand(2).getImm() == AddOffset ||
52 MI->getOperand(2).getImm() == -AddOffset);
56 unsigned AluCode = MI->getOperand(3).getImm();
61 unsigned AluCode = MI->getOperand(3).getImm();
66 if (MI->getOperand(2).getImm() < 0)
77 << getRegisterName(MI->getOperand(1).getReg()) << "], %"
78 << getRegisterName(MI->getOperand(0).getReg());
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI)
84 << "], %" << getRegisterName(MI->getOperand(0).getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMInstPrinter.cpp | 100 const MCOperand &Dst = MI->getOperand(0);
101 const MCOperand &MO1 = MI->getOperand(1);
102 const MCOperand &MO2 = MI->getOperand(2);
103 const MCOperand &MO3 = MI->getOperand(3);
123 const MCOperand &Dst = MI->getOperand(0);
124 const MCOperand &MO1 = MI->getOperand(1);
125 const MCOperand &MO2 = MI->getOperand(2);
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
164 if (MI->getOperand(2).getReg() == ARM::SP &&
165 MI->getOperand(3).getImm() == -4)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| GISelKnownBits.cpp | 38 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
40 int FrameIdx = MI->getOperand(1).getIndex();
53 return getKnownBits(MI.getOperand(0).getReg());
171 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts,
191 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?");
205 const MachineOperand &Src = MI.getOperand(Idx);
240 int FrameIdx = MI.getOperand(1).getIndex();
245 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
247 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
254 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZInstPrinter.cpp | 79 int64_t Value = MI->getOperand(OpNum).getImm();
86 int64_t Value = MI->getOperand(OpNum).getImm();
158 const MCOperand &MO = MI->getOperand(OpNum);
174 const MCOperand &MO = MI->getOperand(OpNum + 1);
192 printOperand(MI->getOperand(OpNum), &MAI, O);
197 printAddress(&MAI, MI->getOperand(OpNum).getReg(),
198 MI->getOperand(OpNum + 1).getImm(), 0, O);
203 printAddress(&MAI, MI->getOperand(OpNum).getReg(),
204 MI->getOperand(OpNum + 1).getImm(),
205 MI->getOperand(OpNum + 2).getReg(), O)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineNegator.cpp | 124 std::array<Value *, 2> Ops{I->getOperand(0), I->getOperand(1)};
125 if (I->isCommutative() && InstCombiner::getComplexity(I->getOperand(0)) <
126 InstCombiner::getComplexity(I->getOperand(1)))
192 if (match(I->getOperand(1), m_APInt(Op1Val)) && *Op1Val == BitWidth - 1) {
194 ? Builder.CreateLShr(I->getOperand(0), I->getOperand(1))
195 : Builder.CreateAShr(I->getOperand(0), I->getOperand(1));
211 if (I->getOperand(0)->getType()->isIntOrIntVectorTy(1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 79 return Instr->getOperand(2).getReg() != ARM::PC;
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC;
|
| MVETPAndVPTOptimisationsPass.cpp | 98 MI->getOperand(1).getReg().isVirtual())
99 MI = MRI->getVRegDef(MI->getOperand(1).getReg());
119 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) {
124 T.getOperand(2).getMBB() == Header) {
148 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI);
157 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI);
160 (LoopPhi->getOperand(2).getMBB() != Latch &&
161 LoopPhi->getOperand(4).getMBB() != Latch)) {
167 Register StartReg = LoopPhi->getOperand(2).getMBB() == Latch
168 ? LoopPhi->getOperand(3).getReg(
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 75 while (!MI.getOperand(i).isFI()) {
81 int FrameIndex = MI.getOperand(i).getIndex();
88 MI.getOperand(i).ChangeToRegister(FrameReg, false);
89 Register reg = MI.getOperand(i - 1).getReg();
97 MI.getOperand(i + 1).getImm();
108 Register reg = MI.getOperand(i - 1).getReg();
119 MI.getOperand(i).ChangeToRegister(FrameReg, false);
120 MI.getOperand(i + 1).ChangeToImmediate(Offset);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 137 MachineOperand &Dst = MI.getOperand(0);
138 MachineOperand &Src = MI.getOperand(1);
154 MachineOperand &Dst = MI.getOperand(0);
155 MachineOperand &Src1 = MI.getOperand(1);
156 MachineOperand &Src2 = MI.getOperand(2);
171 MachineOperand &Dst = MI.getOperand(0);
172 MachineOperand &Src1 = MI.getOperand(1);
173 MachineOperand &Src2 = MI.getOperand(2);
185 MachineOperand &Dst = MI.getOperand(0);
186 MachineOperand &Src = MI.getOperand(1)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 62 assert(Inst.getOperand(2).isImm());
64 int64_t Shift = Inst.getOperand(2).getImm();
70 Inst.getOperand(2).setImm(Shift);
95 unsigned RegOp0 = Inst.getOperand(0).getReg();
96 unsigned RegOp1 = Inst.getOperand(1).getReg();
116 Inst.getOperand(0).setReg(RegOp1);
117 Inst.getOperand(1).setReg(RegOp0);
239 const MCOperand &MO = MI.getOperand(OpNo);
261 const MCOperand &MO = MI.getOperand(OpNo);
283 const MCOperand &MO = MI.getOperand(OpNo)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerLowering.cpp | 221 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
222 Register Dst = MI.getOperand(0).getReg();
223 Register Src = MI.getOperand(1).getReg();
251 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
252 Register Dst = MI.getOperand(0).getReg();
257 Register V1 = MI.getOperand(1).getReg();
258 Register V2 = MI.getOperand(2).getReg();
272 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask();
273 Register Dst = MI.getOperand(0).getReg();
278 Register V1 = MI.getOperand(1).getReg()
[all...] |
