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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AllocationOrder.cpp 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
AllocationOrder.h 111 ArrayRef<MCPhysReg> getOrder() const { return Order; }
RegAllocBase.cpp 128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC);
BreakFalseDeps.cpp 153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
RegAllocFast.cpp 777 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
830 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
961 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC);
1195 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size();
1196 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size();
CriticalAntiDepBreaker.cpp 402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
RegAllocGreedy.cpp 1077 for (MCRegister PhysReg : Order.getOrder()) {
1161 unsigned OrderLimit = Order.getOrder().size();
1180 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) {
1588 for (auto PhysReg : Order.getOrder()) {
AggressiveAntiDepBreaker.cpp 624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 96 /// getOrder - Returns the preferred allocation order for RC. The order
99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
124 /// the registers in getOrder(RC).
129 /// Get the position of the last cost change in getOrder(RC).
131 /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SDNodeDbgValue.h 218 unsigned getOrder() const { return Order; }
258 unsigned getOrder() const { return Order; }
ScheduleDAGSDNodes.cpp 760 unsigned DVOrder = DV->getOrder();
971 return LHS->getOrder() < RHS->getOrder();
984 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
1010 assert((*DI)->getOrder() >= LastOrder &&
1032 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
SelectionDAGDumper.cpp 837 OS << " DbgVal(Order=" << getOrder() << ')';
  /src/external/apache2/llvm/dist/llvm/include/llvm/Passes/
StandardInstrumentations.h 309 std::vector<std::string> &getOrder() { return Order; }
310 const std::vector<std::string> &getOrder() const { return Order; }
  /src/external/apache2/llvm/dist/llvm/lib/Passes/
StandardInstrumentations.cpp 574 std::vector<std::string>::const_iterator BI = Before.getOrder().begin();
575 std::vector<std::string>::const_iterator BE = Before.getOrder().end();
576 std::vector<std::string>::const_iterator AI = After.getOrder().begin();
577 std::vector<std::string>::const_iterator AE = After.getOrder().end();
697 CFD.getOrder().emplace_back(B.getName());
700 Data.getOrder().emplace_back(F.getName());
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreAllocateWWMRegs.cpp 103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 1042 ArrayRef<Record*> Order = RC.getOrder();
1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
1228 ArrayRef<Record*> Order = RC.getOrder();
1379 ArrayRef<Record*> Elems = RC.getOrder(oi);
1392 if (RC.getOrder(oi).empty())
CodeGenRegisters.h 430 ArrayRef<Record*> getOrder(unsigned No = 0) const {
438 // getOrder(0).
AsmMatcherEmitter.cpp 1223 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1299 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1300 RC.getOrder().end())];
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLowOverheadLoops.cpp 122 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const {
1645 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder();
ARMLoadStoreOptimizer.cpp 589 for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGOpenMPRuntime.h 530 unsigned getOrder() const { return Order; }
CGAtomic.cpp 829 llvm::Value *Order = EmitScalarExpr(E->getOrder());
CGOpenMPRuntime.cpp 3192 GetMDInt(Line), GetMDInt(E.getOrder())};
3206 OrderedEntries[E.getOrder()] = std::make_tuple(&E, Loc, ParentName);
3207 ParentFunctions[E.getOrder()] = ParentName;
3231 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())};
3234 OrderedEntries[E.getOrder()] =
3251 StringRef FnName = ParentFunctions[CE->getOrder()];
  /src/external/apache2/llvm/dist/clang/lib/AST/
StmtPrinter.cpp 1674 PrintExpr(Node->getOrder());

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