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    Searched refs:getPhysRegClass (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreAllocateWWMRegs.cpp 159 const TargetRegisterClass *RC = TRI->getPhysRegClass(PhysReg);
SIRegisterInfo.h 151 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;
SIFixSGPRCopies.cpp 149 : TRI.getPhysRegClass(SrcReg);
156 : TRI.getPhysRegClass(DstReg);
SIRegisterInfo.cpp 118 const TargetRegisterClass *RC = TRI.getPhysRegClass(SuperReg);
2004 SIRegisterInfo::getPhysRegClass(MCRegister Reg) const {
2073 RC = getPhysRegClass(Reg);
2239 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegClass(Reg);
2437 assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32);
GCNHazardRecognizer.cpp 977 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) {
1058 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg())))
SIWholeQuadMode.cpp 583 TRI->hasVectorRegisters(TRI->getPhysRegClass(Reg))) {
1432 Reg.isVirtual() ? MRI->getRegClass(Reg) : TRI->getPhysRegClass(Reg);
AMDGPUTargetTransformInfo.cpp 942 RC = TRI->getPhysRegClass(AssignedReg);
SIInstrInfo.cpp 654 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
660 (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) {
672 RC = RI.getPhysRegClass(DestReg);
861 const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg);
2855 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2872 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
4494 return RI.getPhysRegClass(Reg);
AMDGPUISelDAGToDAG.cpp 564 return TRI->getPhysRegClass(Reg);

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