| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86InstComments.cpp | 251 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg());
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
316 Mul2Name = getRegName(MI->getOperand(2).getReg());
317 Mul1Name = getRegName(MI->getOperand(1).getReg());
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
322 Mul1Name = getRegName(MI->getOperand(1).getReg());
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg());
331 Mul2Name = getRegName(MI->getOperand(2).getReg());
332 Mul1Name = getRegName(MI->getOperand(1).getReg());
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUGlobalISelUtils.cpp | 36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
37 return std::make_pair(Def->getOperand(1).getReg(), Offset);
40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
41 return std::make_pair(Def->getOperand(1).getReg(), Offset);
47 if (mi_match(Def->getOperand(1).getReg(), MRI,
51 return std::make_pair(Base->getOperand(1).getReg(), Offset);
54 return std::make_pair(Base->getOperand(0).getReg(), Offset);
|
| AMDGPURegisterBankInfo.cpp | 122 Register DstReg = MI.getOperand(0).getReg();
123 Register SrcReg = MI.getOperand(1).getReg();
137 MRI.setRegBank(True.getReg(0), *NewBank);
138 MRI.setRegBank(False.getReg(0), *NewBank);
149 Register DstReg = MI.getOperand(0).getReg();
160 Register Reg = Op.getReg();
309 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg();
314 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI);
469 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
495 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI)
[all...] |
| AMDGPULegalizerInfo.cpp | 1743 // getreg.
1755 Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1758 .addDef(GetReg)
1760 MRI.setType(GetReg, S32);
1763 return B.buildShl(S32, GetReg, ShiftAmt).getReg(0);
1787 return B.buildLoad(S32, LoadAddr, *MMO).getReg(0);
1796 Register Dst = MI.getOperand(0).getReg();
1797 Register Src = MI.getOperand(1).getReg();
1849 B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src, FlatNull.getReg(0))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| GISelKnownBits.cpp | 38 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
53 return getKnownBits(MI.getOperand(0).getReg());
171 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts,
206 Register SrcReg = Src.getReg();
245 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
247 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
254 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
256 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
266 LLT Ty = MRI.getType(MI.getOperand(1).getReg());
272 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts
[all...] |
| CombinerHelper.cpp | 154 Register DstReg = MI.getOperand(0).getReg();
155 Register SrcReg = MI.getOperand(1).getReg();
159 Register DstReg = MI.getOperand(0).getReg();
160 Register SrcReg = MI.getOperand(1).getReg();
186 Register Reg = MO.getReg();
195 Ops.push_back(BuildVecMO.getReg());
204 assert(MRI.getType(Undef->getOperand(0).getReg()) ==
211 Ops.push_back(Undef->getOperand(0).getReg());
224 Register DstReg = MI.getOperand(0).getReg();
255 LLT DstType = MRI.getType(MI.getOperand(0).getReg());
[all...] |
| InstructionSelector.cpp | 39 if (MO.isReg() && MO.getReg())
40 if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
50 MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
55 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TileShapeInfo.h | 48 if (Row->getReg() == R->getReg() && Col->getReg() == C->getReg())
82 RowImm = GetImm(Row->getReg());
83 ColImm = GetImm(Col->getReg());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 79 return Instr->getOperand(2).getReg() != ARM::PC;
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC;
|
| ARMRegisterBankInfo.cpp | 239 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
274 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());
284 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
297 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
304 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
318 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
319 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
327 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
328 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
337 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyDebugFixup.cpp | 82 if (MO.isReg() && MO.getReg().isValid() &&
83 MFI.isVRegStackified(MO.getReg())) {
90 if (MO.getReg() == Elem.Reg) {
92 LLVM_DEBUG(dbgs() << "Debug Value VReg " << MO.getReg()
109 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) {
112 assert(Prev.Reg == MO.getReg() &&
130 if (MO.isReg() && MFI.isVRegStackified(MO.getReg())) {
131 Stack.push_back({MO.getReg(), nullptr});
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerLowering.cpp | 222 Register Dst = MI.getOperand(0).getReg();
223 Register Src = MI.getOperand(1).getReg();
252 Register Dst = MI.getOperand(0).getReg();
257 Register V1 = MI.getOperand(1).getReg();
258 Register V2 = MI.getOperand(2).getReg();
273 Register Dst = MI.getOperand(0).getReg();
278 Register V1 = MI.getOperand(1).getReg();
279 Register V2 = MI.getOperand(2).getReg();
289 Register Dst = MI.getOperand(0).getReg();
294 Register V1 = MI.getOperand(1).getReg();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
63 .addReg(MI->getOperand(0).getReg())
64 .addReg(MI->getOperand(1).getReg())
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
[all...] |
| SystemZShortenInst.cpp | 78 Register Reg = MI.getOperand(0).getReg();
110 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
120 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
121 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
132 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
134 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
158 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
159 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/ |
| MSP430InstPrinter.cpp | 57 O << getRegisterName(Op.getReg());
81 if (Base.getReg() == MSP430::SR)
92 if ((Base.getReg() != MSP430::SR) &&
93 (Base.getReg() != MSP430::PC))
94 O << '(' << getRegisterName(Base.getReg()) << ')';
100 O << "@" << getRegisterName(Base.getReg());
106 O << "@" << getRegisterName(Base.getReg()) << "+";
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 94 if ( IsVSReg(DstMO.getReg(), MRI) &&
95 !IsVSReg(SrcMO.getReg(), MRI)) {
100 assert((IsF8Reg(SrcMO.getReg(), MRI) ||
101 IsVSSReg(SrcMO.getReg(), MRI) ||
102 IsVSFReg(SrcMO.getReg(), MRI)) &&
115 } else if (!IsVSReg(DstMO.getReg(), MRI) &&
116 IsVSReg(SrcMO.getReg(), MRI)) {
121 assert((IsF8Reg(DstMO.getReg(), MRI) ||
122 IsVSFReg(DstMO.getReg(), MRI) ||
123 IsVSSReg(DstMO.getReg(), MRI)) &
[all...] |
| PPCMacroFusion.cpp | 75 return Op1.getReg() == Op2.getReg();
94 return Register::isVirtualRegister(RA.getReg()) ||
95 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8);
104 if (!Register::isVirtualRegister(RT.getReg()))
108 (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8))
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MachineCopyPropagation.cpp | 123 RegsToInvalidate.insert(MI->getOperand(0).getReg().asMCReg());
124 RegsToInvalidate.insert(MI->getOperand(1).getReg().asMCReg());
146 markRegsUnavailable({MI->getOperand(0).getReg().asMCReg()}, TRI);
157 MCRegister Def = MI->getOperand(0).getReg().asMCReg();
158 MCRegister Src = MI->getOperand(1).getReg().asMCReg();
205 !TRI.isSubRegisterEq(AvailCopy->getOperand(1).getReg(), Reg))
208 Register AvailSrc = AvailCopy->getOperand(1).getReg();
209 Register AvailDef = AvailCopy->getOperand(0).getReg();
229 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg))
234 Register AvailSrc = AvailCopy->getOperand(1).getReg();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMInstPrinter.cpp | 110 printRegName(O, Dst.getReg());
112 printRegName(O, MO1.getReg());
115 printRegName(O, MO2.getReg());
132 printRegName(O, Dst.getReg());
134 printRegName(O, MO1.getReg());
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
164 if (MI->getOperand(2).getReg() == ARM::SP &&
169 printRegName(O, MI->getOperand(1).getReg());
179 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
193 if (MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRRelaxMemOperations.cpp | 100 .addReg(Ptr.getReg());
104 .addReg(Ptr.getReg(), RegState::Define)
105 .addReg(Ptr.getReg())
111 .addReg(Ptr.getReg())
112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill()));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
85 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
97 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
109 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
113 Root.getOperand(0).getReg())
120 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 139 Register DstReg = Dst.getReg();
140 Register SrcReg = Src.getReg();
159 Register DstReg = Dst.getReg();
160 Register SrcReg = Src2.getReg();
176 Register DstReg = Dst.getReg();
177 Register SrcReg = Src1.getReg();
187 Register DstReg = Dst.getReg();
188 Register SrcReg = Src.getReg();
209 Register DstReg = Dst.getReg();
210 Register SrcReg = Src.getReg();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FixupSetCC.cpp | 82 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
104 if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) {
121 TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg())
123 .addReg(MI.getOperand(0).getReg())
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizationArtifactCombiner.h | 57 Register DstReg = MI.getOperand(0).getReg();
58 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
106 Register DstReg = MI.getOperand(0).getReg();
107 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
165 Register DstReg = MI.getOperand(0).getReg();
166 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
222 Register DstReg = MI.getOperand(0).getReg();
223 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
242 const Register MergeSrcReg = SrcMI->getOperand(1).getReg();
286 SrcRegs[i] = SrcMI->getOperand(i + 1).getReg();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVMergeBaseOffset.cpp | 86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
110 MRI->replaceRegWith(Tail.getOperand(0).getReg(),
111 LoADDI.getOperand(0).getReg());
138 Register Rs = TailAdd.getOperand(1).getReg();
139 Register Rt = TailAdd.getOperand(2).getReg();
155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
159 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
181 Register DestReg = LoADDI.getOperand(0).getReg();
[all...] |
