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    Searched refs:getRegBank (Results 1 - 25 of 28) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBankInfo.h 432 RegisterBank &getRegBank(unsigned ID) {
576 const RegisterBank &getRegBank(unsigned ID) const {
577 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
585 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
InstructionSelectorImpl.h 653 RBI.getRegBank(MO.getReg(), MRI, TRI)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64RegisterBankInfo.cpp 53 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
58 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
63 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
253 return getRegBank(AArch64::FPRRegBankID);
273 return getRegBank(AArch64::GPRRegBankID);
275 return getRegBank(AArch64::CCRegBankID);
504 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI);
622 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
623 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
693 (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank |
    [all...]
AArch64InstructionSelector.cpp 645 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
835 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
836 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
860 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
861 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
1046 assert(RBI.getRegBank(False, MRI, TRI)->getID() ==
1047 RBI.getRegBank(True, MRI, TRI)->getID() &&
1056 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) {
1443 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() ==
1732 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenTarget.h 107 /// getRegBank - Return the register bank description.
108 CodeGenRegBank &getRegBank() const;
127 return *getRegBank().getRegClass(R);
RegisterBankEmitter.cpp 215 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
280 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
CodeGenTarget.cpp 335 CodeGenRegBank &CodeGenTarget::getRegBank() const {
398 return getRegBank().getRegistersByName().lookup(Name);
403 const CodeGenRegister *Reg = getRegBank().getReg(R);
405 for (const auto &RC : getRegBank().getRegClasses()) {
420 for (const auto &RC : getRegBank().getRegClasses())
DAGISelMatcherGen.cpp 27 const CodeGenRegister *Reg = T.getRegBank().getReg(R);
29 for (const auto &RC : T.getRegBank().getRegClasses()) {
686 CGP.getTargetInfo().getRegBank().getReg(Def);
732 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank();
898 CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first);
RegisterInfoEmitter.cpp 62 CodeGenRegBank &RegBank = Target.getRegBank();
1063 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
1646 CodeGenRegBank &RegBank = Target.getRegBank();
1664 CodeGenRegBank &RegBank = Target.getRegBank();
FastISelEmitter.cpp 270 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
439 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
AsmMatcherEmitter.cpp 1212 const auto &Registers = Target.getRegBank().getRegisters();
1213 auto &RegClassList = Target.getRegBank().getRegClasses();
2594 const auto &Regs = Target.getRegBank().getRegisters();
2619 const auto &Regs = Target.getRegBank().getRegisters();
CodeGenInstruction.cpp 587 .contains(T.getRegBank().getReg(ADI->getDef())))
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI)
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ARMRegisterBankInfo.cpp 142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
200 return getRegBank(ARM::GPRRegBankID);
207 return getRegBank(ARM::FPRRegBankID);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86RegisterBankInfo.cpp 32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID);
53 return getRegBank(X86::GPRRegBankID);
60 return getRegBank(X86::VECRRegBankID);
X86InstructionSelector.cpp 200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
240 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
643 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
719 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
720 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
848 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
849 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
986 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 283 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
310 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
482 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
514 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
556 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
599 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI);
724 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
730 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI);
731 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI);
1132 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI)
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AMDGPURegisterBankInfo.cpp 124 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI);
150 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI);
205 assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank &&
206 &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank &&
207 &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank);
654 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI);
742 const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI);
841 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI);
1049 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI);
1084 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)
    [all...]
AMDGPURegBankCombiner.cpp 69 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/
MIParser.h 147 const RegisterBank *getRegBank(StringRef Name);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsRegisterBankInfo.cpp 93 return getRegBank(Mips::GPRBRegBankID);
102 return getRegBank(Mips::FPRBRegBankID);
374 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI);
704 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID));
709 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID));
MipsInstructionSelector.cpp 97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBankInfo.cpp 72 const RegisterBank &RegBank = getRegBank(Idx);
83 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
196 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
RegBankSelect.cpp 121 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI);
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/
MIRParser.cpp 569 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value);

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