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    Searched refs:getRegClass (Results 1 - 25 of 202) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsOptionRecord.h 47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
InstructionSelect.cpp 225 auto SrcRC = MRI.getRegClass(SrcReg);
226 auto DstRC = MRI.getRegClass(DstReg);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AllocationOrder.cpp 34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
RegAllocBase.cpp 106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg()))
127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg());
RegAllocFast.cpp 316 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
411 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
465 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
734 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
829 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
960 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1064 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg);
1067 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx);
1078 const TargetRegisterClass *IdxRC = TRI->getRegClass(RCIdx);
1190 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0)
    [all...]
LiveRangeShrink.cpp 194 MRI.getRegClass(DefMO->getReg()) ==
195 MRI.getRegClass(MO.getReg())) {
MachineLoopUtils.cpp 55 R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
DetectDeadLanes.cpp 155 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
251 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
370 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
484 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
LiveRangeEdit.cpp 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
469 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyPeephole.cpp 66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
172 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg))
WebAssemblyMemIntrinsicResults.cpp 171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
WebAssemblyRegColoring.cpp 140 const TargetRegisterClass *RC = MRI->getRegClass(Old);
145 if (MRI->getRegClass(SortedIntervals[C]->reg()) != RC)
WebAssemblyExplicitLocals.cpp 273 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
306 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
378 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
409 typeForRegClass(MRI.getRegClass(Reg)));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TileConfig.cpp 115 unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs();
121 if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID)
174 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));
X86InstructionSelector.cpp 128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
129 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
198 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
201 return getRegClass(Ty, RegBank);
249 getRegClass(MRI.getType(SrcReg), SrcRegBank);
279 getRegClass(MRI.getType(DstReg), DstRegBank);
728 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
729 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
814 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMRegisterBankInfo.cpp 147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) &&
161 assert(RBGPR.covers(*TRI.getRegClass(
164 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
A15SDOptimizer.cpp 139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
271 MRI->getRegClass(MI->getOperand(1).getReg());
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
516 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
517 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
533 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
539 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
640 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
SIMCCodeEmitter.cpp 460 if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
461 MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
462 MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
463 MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
464 MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
465 MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
466 MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
467 MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp 132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
133 MRI.getRegClass(AddendSrcReg))
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
238 MRI.getRegClass(OldFMAReg)))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 134 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
148 ? MRI.getRegClass(SrcReg)
155 ? MRI.getRegClass(DstReg)
199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
223 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
268 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
685 DstRC = MRI->getRegClass(MI.getOperand(0).getReg());
686 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
687 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg());
805 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
RegisterAliasing.cpp 76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXInstrInfo.cpp 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenPredicate.cpp 140 const TargetRegisterClass *RC = MRI->getRegClass(R);
337 if (MRI->getRegClass(PR.R) != PredRC)
436 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
480 if (MRI->getRegClass(DR.R) != PredRC)
482 if (MRI->getRegClass(SR.R) != PredRC)

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