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    Searched refs:getRegClassFor (Results 1 - 25 of 35) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
333 && TLI->getRegClassFor(VT)
334 && TLI->getRegClassFor(VT)->getID() == RCId)
344 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
345 && TLI->getRegClassFor(VT)->getID() == RCId)
482 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
493 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
InstrEmitter.cpp 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
170 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
218 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
281 const TargetRegisterClass *RC = TLI->getRegClassFor(
391 ? TLI->getRegClassFor(OpVT,
464 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
499 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
570 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
FastISel.cpp 324 Reg = createResultReg(TLI.getRegClassFor(VT));
804 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
1415 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1416 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1448 const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
2102 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
FunctionLoweringInfo.cpp 376 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
SelectionDAGISel.cpp 1247 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout()));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
SwiftErrorValueTracking.cpp 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
CallingConvLower.cpp 258 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
MachineScheduler.cpp 2944 TLI->getRegClassFor(LegalIntVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 395 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
405 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
431 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
443 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
503 ResultReg = createResultReg(TLI.getRegClassFor(VT));
592 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
608 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
659 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
965 RC = TLI.getRegClassFor(VT);
977 RC = TLI.getRegClassFor(VT)
    [all...]
ARMISelLowering.h 564 /// getRegClassFor - Return the register class that should be used for the
567 getRegClassFor(MVT VT, bool isDivergent = false) const override;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FastISel.cpp 472 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
2043 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2203 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2344 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2371 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2441 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT);
2500 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64));
2514 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32));
2615 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
2653 ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32))
    [all...]
X86ISelDAGToDAG.cpp 4475 unsigned RegClass = TLI->getRegClassFor(MaskVT)->getID();
4513 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 1630 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1649 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1652 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1845 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1897 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1900 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
2523 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
3666 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3733 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
4071 RC = getRegClassFor(VT)
    [all...]
MipsSEISelDAGToDAG.cpp 1264 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1333 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
MipsFastISel.cpp 1297 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 404 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
417 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
435 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
547 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg);
2874 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);
3107 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
3574 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
3728 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.h 459 getRegClassFor(MVT VT, bool isDivergent) const override;
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 660 const TargetRegisterClass *RC = getRegClassFor(MVT::i64);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 1519 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1524 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 946 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
983 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3210 auto *ARClass = getRegClassFor(SPTy);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 711 getRegClassFor(MVT::i16));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 845 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1191 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 599 getRegClassFor(VA.getLocVT()));
2681 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 846 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {

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