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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RegisterBankEmitter.cpp 183 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
200 BitVector BV(RegisterClassHierarchy.getRegClasses().size());
221 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
253 << RegisterClassHierarchy.getRegClasses().size() << ");\n";
305 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
RegisterInfoEmitter.cpp 135 const auto &RegisterClasses = Bank.getRegClasses();
210 unsigned NumRCs = RegBank.getRegClasses().size();
217 for (const auto &RC : RegBank.getRegClasses()) {
1033 const auto &RegisterClasses = RegBank.getRegClasses();
1184 const auto &RegisterClasses = RegBank.getRegClasses();
1220 const auto &RegisterClasses = RegBank.getRegClasses();
1673 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {
1692 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {
CodeGenTarget.cpp 282 auto &RegClasses = RegBank->getRegClasses();
347 auto &RegClasses = RegBank.getRegClasses();
405 for (const auto &RC : getRegBank().getRegClasses()) {
420 for (const auto &RC : getRegBank().getRegClasses())
CodeGenRegisters.h 715 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
717 const std::list<CodeGenRegisterClass> &getRegClasses() const {
CodeGenRegisters.cpp 940 auto &RegClasses = RegBank.getRegClasses();
1003 auto &RegClasses = RegBank.getRegClasses();
1605 for (auto &RegClass : RegBank.getRegClasses()) {
1889 auto &RegClasses = getRegClasses();
2342 for (const auto &RC : getRegClasses()) {
2383 for (const auto &RC : getRegClasses()) {
DAGISelMatcherGen.cpp 29 for (const auto &RC : T.getRegBank().getRegClasses()) {
AsmMatcherEmitter.cpp 1213 auto &RegClassList = Target.getRegBank().getRegClasses();

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