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    Searched refs:getRegSlot (Results 1 - 25 of 25) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveIntervals.cpp 244 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
255 Indexes->getInstructionIndex(MBB.back()).getRegSlot());
480 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
585 SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
879 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
881 LiveRange::Segment S(SlotIndex(getInstructionIndex(startInst).getRegSlot()),
1131 Prev->end = NewIdx.getRegSlot();
1141 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());
1163 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1175 = LR.advanceTo(OldIdxOut, NewIdx.getRegSlot());
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LiveRangeEdit.cpp 109 OrigIdx = OrigIdx.getRegSlot(true);
110 UseIdx = UseIdx.getRegSlot(true);
177 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
247 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
264 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
PHIElimination.cpp 392 DestCopyIndex.getRegSlot(),
405 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
411 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
412 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
414 DestVNI->def = DestCopyIndex.getRegSlot();
596 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
LiveIntervalCalc.cpp 46 Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
198 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
InlineSpiller.cpp 389 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
390 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
482 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
484 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
535 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
584 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
798 SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
806 Idx = Idx.getRegSlot(true);
919 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
1073 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
    [all...]
RenameIndependentSubregs.cpp 190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
336 SlotIndex RegDefIdx = DefIdx.getRegSlot();
RegisterCoalescer.cpp 607 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
635 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
818 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
823 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
923 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
944 SlotIndex DefIdx = UseIdx.getRegSlot();
975 SlotIndex AIdx = CopyIdx.getRegSlot(true);
1096 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
1166 SlotIndex InsPosIdx = LIS->getInstructionIndex(*InsPos).getRegSlot(true);
1179 LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
    [all...]
RegisterPressure.cpp 315 return LIS->getInstructionIndex(*IdxPos).getRegSlot();
801 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
867 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
887 SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
1048 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1233 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
1262 return S != nullptr && S->end == Pos.getRegSlot();
1273 return S != nullptr && S->start < Pos.getRegSlot(true) &&
1289 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
SplitKit.cpp 180 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
535 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
557 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
629 Def = Indexes.insertMachineInstrInMaps(*ImplicitDef, Late).getRegSlot();
883 AtBegin ? SlotIndex() : LIS.getInstructionIndex(*MBBI).getRegSlot();
1337 Idx = Idx.getRegSlot(MO.isEarlyClobber());
1360 Idx = Idx.getRegSlot(true);
LiveDebugVariables.cpp 898 : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
1006 LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
1013 const VNInfo *DstVNI = DstLI->getVNInfoAt(Idx.getRegSlot());
1014 assert(DstVNI && DstVNI->def == Idx.getRegSlot() && "Bad copy value");
TwoAddressInstructionPass.cpp 1430 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
1436 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
1499 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
LiveInterval.cpp 994 SlotIndex Pos = Indexes.getInstructionIndex(MI).getRegSlot(EarlyClobber);
MachineVerifier.cpp 2073 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2077 if (stores && !LI.liveAt(Idx.getRegSlot())) {
2287 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
MachineScheduler.cpp 1425 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1459 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegAllocGreedy.cpp 2273 llvm::lower_bound(RMS, Uses.front().getRegSlot()) - RMS.begin();
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyMemIntrinsicResults.cpp 94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot();
128 Indices.push_back(WhereIdx.getRegSlot());
WebAssemblyOptimizeLiveIntervals.cpp 113 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
WebAssemblyRegStackify.cpp 293 LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot());
541 LI.removeSegment(LIS.getInstructionIndex(*Def).getRegSlot(),
542 LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
591 SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
649 SlotIndex TeeIdx = LIS.InsertMachineInstrInMaps(*Tee).getRegSlot();
650 SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot();
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TileConfig.cpp 187 LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp 282 VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
325 FMAIdx.getRegSlot());
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
SlotIndexes.h 254 SlotIndex getRegSlot(bool EC = false) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineScheduler.cpp 299 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
361 isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(),
362 LIS->getInstructionIndex(*EndBlock).getRegSlot(), MRI,
GCNIterativeScheduler.cpp 383 auto SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
GCNSchedStrategy.cpp 437 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 1010 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();

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