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    Searched refs:getRegState (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZPostRewrite.cpp 124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
UnreachableBlockElim.cpp 194 .addReg(InputReg, getRegState(Input), InputSub);
MachinePipeliner.cpp 406 .addReg(RegOp.getReg(), getRegState(RegOp),
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSplitDouble.cpp 638 unsigned RSA = getRegState(AdrOp);
742 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
750 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
765 unsigned RS = getRegState(Op1);
799 unsigned RS = getRegState(Op1);
919 unsigned RS1 = getRegState(Op1);
920 unsigned RS2 = getRegState(Op2);
HexagonExpandCondsets.cpp 640 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
644 unsigned SrcState = getRegState(SrcOp);
697 unsigned S = getRegState(ST);
886 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
HexagonInstrInfo.cpp 1093 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1115 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1131 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1133 .addReg(SrcOp.getReg(), getRegState(SrcOp))
1148 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1153 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1286 unsigned PState = getRegState(Op1);
1319 unsigned PState = getRegState(Op1);
HexagonConstPropagation.cpp 3005 .addReg(R1.Reg, getRegState(Acc), R1.SubReg);
3035 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg())
3036 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg())
3071 .addReg(SR.Reg, getRegState(SO), SR.SubReg);
3103 .addReg(SR.Reg, getRegState(SO), SR.SubReg);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBuilder.h 528 inline unsigned getRegState(const MachineOperand &RegOp) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMConstantIslandPass.cpp 1990 getRegState(Cmp.MI->getOperand(0)))
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 4764 unsigned MaskState = getRegState(MIB->getOperand(1));

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