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Searched
refs:getSUnit
(Results
1 - 25
of
28
) sorted by relevancy
1
2
/src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNMinRegStrategy.cpp
90
for (auto PDep : SDep.
getSUnit
()->Preds) {
91
auto PSU = PDep.
getSUnit
();
180
if (S.
getSUnit
()->isBoundaryNode() || isScheduled(S.
getSUnit
()) ||
183
for (const auto &P : S.
getSUnit
()->Preds) {
184
auto PSU = P.
getSUnit
();
196
if (!P.
getSUnit
()->isBoundaryNode() && !isScheduled(P.
getSUnit
()) &&
197
Set.insert(P.
getSUnit
()).second)
198
Worklist.push_back(P.
getSUnit
());
[
all
...]
AMDGPUExportClustering.cpp
70
SUnit *PredSU = Pred.
getSUnit
();
86
SUnit *PredSU = Pred.
getSUnit
();
95
SUnit *ExportPredSU = ExportPred.
getSUnit
();
130
removeExportDependencies(DAG, *Succ.
getSUnit
());
SIMachineScheduler.cpp
425
if (BC->isSUInBlock(Succ.
getSUnit
(), ID))
435
SUnit *SuccSU = SuccEdge->
getSUnit
();
445
SUnit *SuccSU = SuccEdge->
getSUnit
();
466
SUnit *SuccSU = Succ.
getSUnit
();
499
NodeNum2Index.find(Succ.
getSUnit
()->NodeNum);
647
if (PredDep.
getSUnit
() == &FromSU &&
802
SUnit *Pred = PredDep.
getSUnit
();
844
SUnit *Succ = SuccDep.
getSUnit
();
928
SUnit *Succ = SuccDep.
getSUnit
();
998
SUnit *Succ = SuccDep.
getSUnit
();
[
all
...]
GCNILPSched.cpp
66
SUnit *PredSU = Pred.
getSUnit
();
110
unsigned Height = Succ.
getSUnit
()->getHeight();
277
auto PredSU = PredEdge.
getSUnit
();
AMDGPUSubtarget.cpp
876
const SUnit *SU = SI.
getSUnit
();
889
if (SI.
getSUnit
() != SU && !Visited.count(SI.
getSUnit
()))
890
Preds.push_back(SI.
getSUnit
());
915
SUnit *SUv = SI.
getSUnit
();
921
SUnit *Succ = SI.
getSUnit
();
/src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ScheduleDAG.cpp
112
if (!Required && PredDep.
getSUnit
() == D.
getSUnit
())
118
SUnit *PredSU = PredDep.
getSUnit
();
136
SUnit *N = D.
getSUnit
();
183
SUnit *N = D.
getSUnit
();
225
SUnit *SuccSU = SuccDep.
getSUnit
();
240
SUnit *PredSU = PredDep.
getSUnit
();
273
SUnit *PredSU = PredDep.
getSUnit
();
304
SUnit *SuccSU = SuccDep.
getSUnit
();
330
unsigned MaxDepth = BestI->
getSUnit
()->getDepth()
[
all
...]
LatencyPriorityQueue.cpp
59
SUnit &Pred = *P.
getSUnit
();
78
if (getSingleUnscheduledPred(I->
getSUnit
()) == SU)
93
AdjustPriorityOfUnscheduledPreds(Succ.
getSUnit
());
MacroFusion.cpp
42
return SI.
getSUnit
();
84
if (SI.
getSUnit
() == &SecondSU)
88
if (SI.
getSUnit
() == &FirstSU)
101
SUnit *SU = SI.
getSUnit
();
114
SUnit *SU = SI.
getSUnit
();
183
SUnit &DepSU = *Dep.
getSUnit
();
MachinePipeliner.cpp
626
NewInstrChanges[KV.first] = InstrChanges[
getSUnit
(KV.first)];
693
SUnit *SuccSU = SI.
getSUnit
();
861
SUnit *SU =
getSUnit
(UseMI);
881
SUnit *SU =
getSUnit
(DefMI);
902
MachineInstr *PMI = PI.
getSUnit
()->getInstr();
936
SUnit *DefSU =
getSUnit
(DefMI);
943
SUnit *LastSU =
getSUnit
(LastMI);
953
if (P.
getSUnit
() == DefSU)
956
Topo.RemovePred(&I, Deps[i].
getSUnit
());
962
if (P.
getSUnit
() == &I && P.getKind() == SDep::Order
[
all
...]
ScheduleDAGInstrs.cpp
1211
if (Topo.IsReachable(PredDep.
getSUnit
(), SuccSU))
1213
Topo.AddPredQueued(SuccSU, PredDep.
getSUnit
());
1289
unsigned PredNum = PredDep.
getSUnit
()->NodeNum;
1317
+= R.DFSNodeData[PredDep.
getSUnit
()->NodeNum].InstrCount;
1323
ConnectionPairs.push_back(std::make_pair(PredDep.
getSUnit
(), Succ));
1370
const SUnit *PredSU = PredDep.
getSUnit
();
1446
!SuccDep.
getSUnit
()->isBoundaryNode())
1473
|| PredDep.
getSUnit
()->isBoundaryNode()) {
1477
if (Impl.isVisited(PredDep.
getSUnit
())) {
1481
Impl.visitPreorder(PredDep.
getSUnit
());
[
all
...]
AggressiveAntiDepBreaker.cpp
277
const SUnit *PredSU = Pred.
getSUnit
();
290
return (Next) ? Next->
getSUnit
() : nullptr;
844
SUnit *NextSU = Edge->
getSUnit
();
887
if (Pred.
getSUnit
() == NextSU ? (Pred.getKind() != SDep::Anti ||
896
if ((Pred.
getSUnit
() == NextSU) && (Pred.getKind() != SDep::Anti) &&
901
} else if ((Pred.
getSUnit
() != NextSU) &&
MachineScheduler.cpp
638
SUnit *SuccSU = SuccEdge->
getSUnit
();
675
SUnit *PredSU = PredEdge->
getSUnit
();
931
if (SUnit *SU =
getSUnit
(&MI))
1352
const SUnit *DefSU =
getSUnit
(DefMI);
1650
if (Succ.
getSUnit
() == SUb)
1652
LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.
getSUnit
()->NodeNum
1654
DAG->addEdge(Succ.
getSUnit
(), SDep(SUb, SDep::Artificial));
1664
if (Pred.
getSUnit
() == SUa)
1666
LLVM_DEBUG(dbgs() << " Copy Pred SU(" << Pred.
getSUnit
()->NodeNum
1668
DAG->addEdge(SUa, SDep(Pred.
getSUnit
(), SDep::Artificial))
[
all
...]
CriticalAntiDepBreaker.cpp
146
const SUnit *PredSU = P.
getSUnit
();
560
const SUnit *NextSU = Edge->
getSUnit
();
583
if (P.
getSUnit
() == NextSU
/src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHazardRecognizer.cpp
145
S.
getSUnit
()->NumPredsLeft == 1) {
146
UsesDotCur = S.
getSUnit
();
160
TII->mayBeNewStore(*S.
getSUnit
()->getInstr()) &&
161
Resources->canReserveResources(*S.
getSUnit
()->getInstr())) {
162
PrefVectorStoreNew = S.
getSUnit
();
HexagonSubtarget.cpp
225
MachineInstr &MI2 = *SI.
getSUnit
()->getInstr();
232
for (SDep &PI : SI.
getSUnit
()->Preds) {
233
if (PI.
getSUnit
() != &SU || PI.getKind() != SDep::Order)
236
SI.
getSUnit
()->setDepthDirty();
419
MachineInstr *DDst = Dst->Succs[0].
getSUnit
()->getInstr();
492
if (!I.isAssignedRegDep() || I.
getSUnit
() != Dst)
540
if (!I.isAssignedRegDep() || I.
getSUnit
() != Dst)
557
!I.
getSUnit
()->getInstr()->isPseudo())
558
return I.
getSUnit
();
635
if (ExclSrc.count(I.
getSUnit
()) == 0 &
[
all
...]
HexagonMachineScheduler.cpp
86
if (S.
getSUnit
() == SUu && S.getLatency() > 0)
293
unsigned PredReadyCycle = PI.
getSUnit
()->TopReadyCycle;
312
unsigned SuccReadyCycle = I->
getSUnit
()->BotReadyCycle;
527
if (!Pred.
getSUnit
()->isScheduled && (Pred.
getSUnit
() != SU2))
542
if (!Succ.
getSUnit
()->isScheduled && (Succ.
getSUnit
() != SU2))
647
if (isSingleUnscheduledPred(SI.
getSUnit
(), SU))
653
if (isSingleUnscheduledSucc(PI.
getSUnit
(), SU))
707
if (!PI.
getSUnit
()->getInstr()->isPseudo() && PI.isAssignedRegDep() &
[
all
...]
HexagonVLIWPacketizer.cpp
938
if (Dep.
getSUnit
() == PacketSUDep && Dep.getKind() == SDep::Anti &&
1006
if (Dep.
getSUnit
() == SU && Dep.getKind() == SDep::Data &&
1407
if (SUJ->Succs[i].
getSUnit
() != SUI)
1928
if (Pred.
getSUnit
() == SUJ)
1939
if (Pred.
getSUnit
() == SUJ && Pred.getLatency() > 1)
/src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp
226
Topo.AddPredQueued(SU, D.
getSUnit
());
234
Topo.AddPred(SU, D.
getSUnit
());
242
Topo.RemovePred(SU, D.
getSUnit
());
399
SUnit *PredSU = PredEdge->
getSUnit
();
564
assert((!RegDef || RegDef == SU || RegDef == Pred.
getSUnit
()) &&
566
LiveRegDefs[Pred.getReg()] = Pred.
getSUnit
();
821
SUnit *PredSU = PredEdge->
getSUnit
();
843
assert(LiveRegDefs[Pred.getReg()] == Pred.
getSUnit
() &&
899
LiveRegGens[Reg] = Succ.
getSUnit
();
902
Succ2.
getSUnit
()->getHeight() < LiveRegGens[Reg]->getHeight()
[
all
...]
ResourcePriorityQueue.cpp
77
SUnit *PredSU = Pred.
getSUnit
();
115
SUnit *SuccSU = Succ.
getSUnit
();
217
SUnit &PredSU = *Pred.
getSUnit
();
234
if (getSingleUnscheduledPred(Succ.
getSUnit
()) == SU)
278
if (Succ.
getSUnit
() == SU)
503
if (Pred.isCtrl() || (Pred.
getSUnit
()->NumRegDefsLeft == 0))
505
--Pred.
getSUnit
()->NumRegDefsLeft;
518
adjustPriorityOfUnscheduledPreds(Succ.
getSUnit
());
ScheduleDAGFast.cpp
140
SUnit *PredSU = PredEdge->
getSUnit
();
171
LiveRegDefs[Pred.getReg()] = Pred.
getSUnit
();
194
if (LiveRegCycles[Succ.getReg()] == Succ.
getSUnit
()->getHeight()) {
285
else if (Pred.
getSUnit
()->getNode() &&
286
Pred.
getSUnit
()->getNode()->isOperandOf(LoadNode))
298
if (ChainPred.
getSUnit
()) {
317
SUnit *SuccDep = D.
getSUnit
();
325
SUnit *SuccDep = D.
getSUnit
();
362
SUnit *SuccSU = Succ.
getSUnit
();
398
SUnit *SuccSU = Succ.
getSUnit
();
[
all
...]
ScheduleDAGVLIW.cpp
114
SUnit *SuccSU = D.
getSUnit
();
/src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp
39
const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].
getSUnit
());
47
if (SU->Preds[i].
getSUnit
() == CurGroup[j])
65
const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].
getSUnit
());
73
if (SU->Preds[i].
getSUnit
() == CurGroup[j])
/src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h
286
SUnit *
getSUnit
(MachineInstr *MI) const;
390
inline SUnit *ScheduleDAGInstrs::
getSUnit
(MachineInstr *MI) const {
ScheduleDAG.h
152
SUnit *
getSUnit
() const;
433
if (Pred.
getSUnit
() == N)
441
if (Succ.
getSUnit
() == N)
480
inline SUnit *SDep::
getSUnit
() const { return Dep.getPointer(); }
636
return Node->Preds[Operand].
getSUnit
();
MachinePipeliner.h
243
return Source->getInstr()->isPHI() || Dep.
getSUnit
()->getInstr()->isPHI();
330
auto SuccSUnit = Succ.
getSUnit
();
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Indexes created Sat Jun 06 00:24:59 UTC 2026