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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetSchedule.cpp 110 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
135 unsigned SchedClass = MI->getDesc().getSchedClass();
198 unsigned DefClass = DefMI->getDesc().getSchedClass();
262 unsigned SCIdx = TII->get(Opcode).getSchedClass();
327 unsigned SchedClass = MI->getDesc().getSchedClass();
340 unsigned SchedClass = TII->get(Opcode).getSchedClass();
DFAPacketizer.cpp 58 unsigned Action = ItinActions[MID->getSchedClass()];
59 if (MID->getSchedClass() == 0 || Action == 0)
67 unsigned Action = ItinActions[MID->getSchedClass()];
68 if (MID->getSchedClass() == 0 || Action == 0)
ScoreboardHazardRecognizer.cpp 128 unsigned idx = MCID->getSchedClass();
187 unsigned idx = MCID->getSchedClass();
TargetInstrInfo.cpp 1098 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1101 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1113 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1125 unsigned Class = MI.getDesc().getSchedClass();
1159 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1169 unsigned DefClass = DefMI.getDesc().getSchedClass();
1262 unsigned DefClass = DefMI.getDesc().getSchedClass();
1263 unsigned UseClass = UseMI.getDesc().getSchedClass();
MachineCombiner.cpp 394 unsigned Idx = TII->get(Opc).getSchedClass();
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZHazardRecognizer.cpp 47 const MCSchedClassDesc *SC = getSchedClass(SU);
93 const MCSchedClassDesc *SC = getSchedClass(SU);
171 const MCSchedClassDesc *SC = getSchedClass(SU);
272 const MCSchedClassDesc *SC = getSchedClass(SU);
341 const MCSchedClassDesc *SC = getSchedClass(SU);
390 const MCSchedClassDesc *SC = getSchedClass(SU);
SystemZHazardRecognizer.h 121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
SystemZMachineScheduler.cpp 255 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU);
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCSchedule.cpp 70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64StorePairSuppress.cpp 85 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
AArch64SIMDInstrOpt.cpp 228 unsigned SCIdx = InstDesc->getSchedClass();
243 IDesc->getSchedClass());
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
InstructionInfoView.cpp 102 unsigned SchedClassID = MCDesc.getSchedClass();
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 182 unsigned SCClass = Desc.getSchedClass();
209 unsigned SCClass = Desc.getSchedClass();
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
90 unsigned IIC = MCID->getSchedClass();
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 265 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCInstrDesc.h 612 unsigned getSchedClass() const { return SchedClass; }
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SchedClassResolution.cpp 235 unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
SubtargetEmitter.cpp 597 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
1305 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
1313 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1578 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC);
1620 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
1623 emitPredicates(*FinalT, SchedModels.getSchedClass(FinalT->ToClassIdx),
CodeGenSchedule.h 541 CodeGenSchedClass &getSchedClass(unsigned Idx) {
545 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
CodeGenSchedule.cpp 909 CodeGenSchedClass &SC = getSchedClass(SCIdx);
1662 << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "("
1687 const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
1702 SchedModels.getSchedClass(FromClassIdx)
1998 const CodeGenSchedClass &SC = getSchedClass(SCIdx);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
Instruction.h 263 unsigned getSchedClass() const { return RD->SchedClassID; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInstrInfo.cpp 428 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
447 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
458 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/
llvm-exegesis.cpp 337 State.getInstrInfo().get(Opcode).getSchedClass() == 0) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 2182 unsigned SchedClass = MI.getDesc().getSchedClass();
2374 unsigned SchedClass = MI.getDesc().getSchedClass();
2623 unsigned SchedClass = MI.getDesc().getSchedClass();
2628 unsigned SchedClass = MI.getDesc().getSchedClass();
2633 unsigned SchedClass = MI.getDesc().getSchedClass();
2638 unsigned SchedClass = MI.getDesc().getSchedClass();
4209 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4514 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4581 << " Class: " << NewMI->getDesc().getSchedClass());
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
InstrBuilder.cpp 521 unsigned SchedClassID = MCDesc.getSchedClass();

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