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    Searched refs:getSchedModel (Results 1 - 25 of 35) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetSubtargetInfo.cpp 53 return getSchedModel().PostRAScheduler;
TargetSchedule.cpp 65 SchedModel = TSInfo->getSchedModel();
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SchedClassResolution.cpp 53 const auto &SM = STI.getSchedModel();
210 SCDesc(STI.getSchedModel().getSchedClassDesc(ResolvedSchedClassId)),
214 STI.getSchedModel(), NonRedundantWriteProcRes)) {
223 const auto &SM = STI.getSchedModel();
236 const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel()
252 const auto &SchedModel = STI.getSchedModel();
Analysis.cpp 142 SubtargetInfo_->getSchedModel().getSchedClassDesc(SchedClassId);
383 const auto &SM = SubtargetInfo_->getSchedModel();
419 writeEscaped<kEscapeHtml>(OS, SubtargetInfo_->getSchedModel()
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
RegisterFileStatistics.cpp 22 const MCSchedModel &SM = STI.getSchedModel();
121 assert(STI.getSchedModel().hasExtraProcessorInfo() &&
124 STI.getSchedModel().getExtraProcessorInfo();
InstructionView.cpp 40 const MCSchedModel &SM = STI.getSchedModel();
SchedulerStatistics.cpp 22 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0),
25 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) {
ResourcePressureView.cpp 27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
109 const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
153 printColumnNames(FOS, getSubTargetInfo().getSchedModel());
InstructionInfoView.cpp 95 const MCSchedModel &SM = STI.getSchedModel();
TimelineView.cpp 46 const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
170 getSubTargetInfo().getSchedModel().MicroOpBufferSize);
BottleneckAnalysis.cpp 446 : InstructionView(sti, Printer, S), Tracker(sti.getSchedModel()),
613 const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
  /src/external/apache2/llvm/dist/llvm/lib/MCA/
Context.cpp 33 const MCSchedModel &SM = STI.getSchedModel();
73 const MCSchedModel &SM = STI.getSchedModel();
InstrBuilder.cpp 33 const MCSchedModel &SM = STI.getSchedModel();
35 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
42 const MCSchedModel &SM = STI.getSchedModel();
253 const MCSchedModel &SM = STI.getSchedModel();
512 assert(STI.getSchedModel().hasInstrSchedModel() &&
518 const MCSchedModel &SM = STI.getSchedModel();
627 unsigned ProcID = STI.getSchedModel().getProcessorID();
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCSchedule.cpp 91 const MCSchedModel &SM = STI.getSchedModel();
MCSubtargetInfo.cpp 334 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
DispatchStage.cpp 35 DispatchWidth = Subtarget.getSchedModel().IssueWidth;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCSubtarget.cpp 192 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/
llvm-mca.cpp 344 bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder();
350 if (!STI->getSchedModel().hasInstrSchedModel()) {
356 if (STI->getSchedModel().InstrItineraries)
460 const MCSchedModel &SM = STI->getSchedModel();
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 262 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
MachinePipeliner.h 450 : STI(ST), SM(ST->getSchedModel()), UseDFA(ST->useDFAforSMS()),
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCSubtargetInfo.h 162 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp 255 SchedModel = DAG->getSchedModel();
262 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries();
272 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
273 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
  /src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
RegisterFile.cpp 479 const MCSchedModel &SM = STI.getSchedModel();
559 const MCSchedModel &SM = STI.getSchedModel();
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 198 const MCSchedModel SCModel = STI->getSchedModel();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInstrInfo.cpp 427 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
446 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
457 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;

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