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    Searched refs:getSubReg (Results 1 - 25 of 140) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 211 Src0 = TRI.getSubReg(Src0, SubRegIndex);
212 Src1 = TRI.getSubReg(Src1, SubRegIndex);
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
218 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
SIFoldOperands.cpp 318 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
510 !Sub->getSubReg() && TII->isFoldableCopy(*SubDef);
567 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) {
616 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
634 if (RSUse.getSubReg() != RegSeqDstSubReg)
740 !UseMI->getOperand(1).getSubReg()) {
745 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
883 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
915 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
923 if (UseOp.getSubReg() == AMDGPU::sub0)
    [all...]
SIOptimizeExecMaskingPreRA.cpp 140 unsigned CmpSubReg = AndCC->getSubReg();
144 CmpSubReg = AndCC->getSubReg();
163 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS);
193 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
SIFrameLowering.cpp 166 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0);
167 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1);
229 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0);
230 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1);
267 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
268 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
528 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
529 Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
569 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
570 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCRegisterInfo.cpp 27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSplitConst32AndConst64.cpp 89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
HexagonRDFOpt.cpp 124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
RDFCopy.cpp 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
128 return S.getSubReg();
HexagonSplitDouble.cpp 259 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
320 if (!Op.getSubReg())
324 if (MI->getOperand(1).getSubReg() != 0)
443 if (Op.getSubReg())
603 unsigned SR = Op.getSubReg();
649 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
652 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
658 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
674 assert(!UpdOp.getSubReg() && "Def operand with subreg")
    [all...]
HexagonAsmPrinter.cpp 136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
540 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
541 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
552 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
553 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
566 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
567 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
HexagonExpandCondsets.cpp 180 Sub(Op.getSubReg()) {}
325 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
377 Register DR = Op.getReg(), DSR = Op.getSubReg();
594 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
649 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
650 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
654 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
676 Register DR = MD.getReg(), DSR = MD.getSubReg();
886 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
888 PredOp.getSubReg());
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VERegisterInfo.cpp 166 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);
167 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);
181 Register DestHiReg = getSubReg(DestReg, VE::sub_even);
182 Register DestLoReg = getSubReg(DestReg, VE::sub_odd);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CalcSpillWeights.cpp 52 Sub = MI->getOperand(0).getSubReg();
54 HSub = MI->getOperand(1).getSubReg();
56 Sub = MI->getOperand(1).getSubReg();
58 HSub = MI->getOperand(0).getSubReg();
68 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg();
PeepholeOptimizer.cpp 514 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
851 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg());
854 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
897 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
934 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg());
939 if (MODef.getSubReg())
982 if (MOExtractedReg.getSubReg())
990 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1059 if ((Src.SubReg = MOInsertedReg.getSubReg()))
1069 return MODef.getSubReg() == 0
    [all...]
DetectDeadLanes.cpp 159 unsigned SrcSubIdx = MO.getSubReg();
198 unsigned MOSubReg = MO.getSubReg();
294 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
343 assert(Def.getSubReg() == 0 &&
395 unsigned MOSubReg = MO.getSubReg();
409 assert(Def.getSubReg() == 0 &&
424 unsigned SubReg = MO.getSubReg();
457 unsigned SubReg = MO.getSubReg();
OptimizePHIs.cpp 119 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() &&
120 !SrcMI->getOperand(1).getSubReg() &&
UnreachableBlockElim.cpp 176 assert(Output.getSubReg() == 0 && "Cannot have output subregister");
181 unsigned InputSub = Input.getSubReg();
RegAllocFast.cpp 835 unsigned SubRegIdx = MO.getSubReg();
837 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);
866 if (MO.getSubReg() && !MO.isUndef()) {
953 if (MI.isCopy() && MI.getOperand(1).getSubReg() == 0) {
981 if (!MO.getSubReg()) {
988 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister());
1123 if (MO.isTied() || (MO.getSubReg() != 0 && !MO.isUndef()))
1207 (MO0.getSubReg() == 0 && !MO0.isUndef());
1209 (MO1.getSubReg() == 0 && !MO1.isUndef())
    [all...]
TargetInstrInfo.cpp 187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
188 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
189 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
454 if (FoldOp.getSubReg() || LiveOp.getSubReg())
540 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
586 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
932 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
1304 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1330 InputReg.SubReg = MOReg.getSubReg();
    [all...]
ExpandPostRAPseudos.cpp 85 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
LiveIntervalCalc.cpp 68 unsigned SubReg = MO.getSubReg();
168 unsigned SubReg = MO.getSubReg();
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
152 SubReg = MI->getOperand(1).getSubReg();
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 33 MO.getSubReg() == SystemZ::subreg_l32 ||
34 MO.getSubReg() == SystemZ::subreg_hl32)
37 MO.getSubReg() == SystemZ::subreg_h32 ||
38 MO.getSubReg() == SystemZ::subreg_hh32)
114 if (MO->getSubReg())
115 PhysReg = getSubReg(PhysReg, MO->getSubReg());
116 if (VRRegMO->getSubReg())
117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp 221 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
222 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg();
223 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();

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